Fujitsu MB91460 SERIES FR60 Manuel d'utilisateur

FUJITSU SEMICONDUCTORCONTROLLER MANUALFR6032-BIT MICROCONTROLLERMB91460 SeriesUser’s ManualVersion 1.002006-10-22- PRELIMINARY -CM71-xxxxx-1E

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84Chapter 3 MB91460 Series Basic Information6.Pin DefinitionsB15 67 53 P21_5 - SOT1 ^ - TP00_0 U/D CH / A Stop - 4mAC16 66 54 P21_4 - SIN1 ^ - TP00_0

984Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM2.Check for Boot ConditionsFlow Chart of checking boot conditions on MB91V460*1) Boot-Security-Vector

985Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM2.Check for Boot Conditions2.2 Flash devices of MB91460 series (MB91F46x)After the chip initializati

986Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM2.Check for Boot Conditionsthe internal bootloader is entered. Otherwise Boot ROM is left and applica

987Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM2.Check for Boot Conditions2.3 Internal Bootloader DescriptionIf a valid boot condition for entering

988Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM3.Registers modified by Boot ROM3. Registers modified by Boot ROMThe Boot ROM initializes the chip an

989Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM4.Flash Access Mode Switching4. Flash Access Mode SwitchingOn MB91460 series flash devices it is poss

990Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM5.Bootloader Update Strategy5. Bootloader Update StrategySome applications require the possibility o

991Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM5.Bootloader Update StrategyBy use of this bootloader the application as well as user bootloader 2 ca

992Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM5.Bootloader Update Strategy

993Chapter 54 Flash Memory1.OverviewChapter 54 Flash MemoryThis chapter describes the use of the built-in flash memory.1. OverviewThe MB91F46x devic

85Chapter 3 MB91460 Series Basic Information6.Pin DefinitionsJ4 666 557 P26_0 - SMC1P2 AN24 - TP05_0 - CH / A Stop SMC / AN 30mAH3 667 556 P27_7 - SMC

994Chapter 54 Flash Memory3.Configuration3. ConfigurationFigure 3-1 Block Diagram (32bit flash)Figure 3-2 Block Diagram (64bit flash)FLASH memory Con

995Chapter 54 Flash Memory3.Configuration3.1 Address conversion from CPU Mode to Flash Programming ModeFlash memory's address mapping is differe

996Chapter 54 Flash Memory4.Registers4. RegistersFor the description of the Flash related registers, refer to Chapter 11 Memory Controller (Page No

997Chapter 54 Flash Memory6.Flash Access Mode Switching6. Flash Access Mode SwitchingOn MB91460 series flash devices it is possible to switch between

998Chapter 54 Flash Memory6.Flash Access Mode Switching6.1 Flash Memory ModeResetting after setting the MD2, MD1 and MD0 pins to “1”, “1” and “1” wi

999Chapter 54 Flash Memory7.Auto Algorithms7. Auto AlgorithmsWrites and erases to Flash memory are performed by launching the Flash memory's ow

1000Chapter 54 Flash Memory7.Auto Algorithms7.2 Auto Algorithm Commands Read/reset commandIssue a Read/reset command sequence to recover to read m

1001Chapter 54 Flash Memory7.Auto Algorithms Chip eraseChip erase (erase all sectors at once) is performed via six accesses. First, there are two “u

1002Chapter 54 Flash Memory7.Auto Algorithmshas halted, by entering the address of an erased sector, and monitoring the values read from bits 6 and 7

1003Chapter 54 Flash Memory7.Auto Algorithms7.3 Hardware Sequence FlagThis Flash memory performs the write/erase sequence via Auto Algorithms. It th

86Chapter 3 MB91460 Series Basic Information6.Pin DefinitionsU2 624 522 P32_5 - SEG29 SOT15 - TP06_0 - CH / A Stop LCD COM/SEG 4mAT3 623 521 P32_4 - S

1004Chapter 54 Flash Memory7.Auto Algorithms7.4 FLCR: Hardware Sequence Flag• FLCR: Address. Any address in Flash memory. (Access: Byte or half-wor

1005Chapter 54 Flash Memory7.Auto Algorithms• bit 4: Undefined:The read value is indeterminate.• bit 3: Sector erase timer (SETIMR)• During sector er

1006Chapter 54 Flash Memory7.Auto Algorithms7.5 Sample Use of Hardware Sequence FlagIt is possible to determine the state of the Flash memory’s inte

1007Chapter 54 Flash Memory8.Caution8. Caution• Please review the MBM29LV400TC data sheet in conjunction with this document.• CPU modeWhen in CPU mo

1008Chapter 54 Flash Memory8.Caution

1009Chapter 55 Flash Security1.OverviewChapter 55 Flash Security1. Overview• Module for controlling the read and write access protection to the embe

1010Chapter 55 Flash Security3.Flash Security Vectors3. Flash Security Vectors3.1 Vector addressesTwo Flash Security Vectors (FSV1, FSV2) are locat

1011Chapter 55 Flash Security3.Flash Security Vectors FSV1 (bits 15 to 0)The setting of the Flash Security Vector FSV1 bits [15:0] is responsible fo

1012Chapter 55 Flash Security3.Flash Security Vectors3.3 Security Vector FSV2The setting of the Flash Security Vector FSV2 bits [31:0] is responsibl

1013Chapter 55 Flash Security4.Register4. Register4.1 Flash Security Control Register FSCR0: Address 7100h (Access: Byte (write), Word (read))(See

87Chapter 3 MB91460 Series Basic Information6.Pin DefinitionsAG1 567 471 ICLK - - - - TE22_0 - C no Tool 8mAAH1 565 469 ICD_3 - - - - TE21_0 - C no To

1014Chapter 55 Flash Security4.RegisterRemark: The Flash Security Vector Re-Fetch sequence is especially intented to be used after a chip erasecomman

1015Chapter 55 Flash Security4.Register• Bit31-25: Reserved bit. The read value is always “0”.• Bit24: RDY: CRC32 Sequence Ready• Bit23-20: Reserved

1016Chapter 55 Flash Security4.Register

1017Chapter 56 Electrical SpecificationChapter 56 Electrical SpecificationSee the appropriate data sheet for the electrical specification of each devi

1018Chapter 56 Electrical Specification

FR60MB91460 Series Hardware ManualEuropean Microcontroller Design CentreAuthor : MBo

CM71-xxxxx-1EFUJITSU SEMICONDUCTOR • CONTROLLER MANUALFR6032-BIT MICROCONTROLLERMB91460 SeriesUser's ManualJan 2005 the zero editionPublished FUJ

88Chapter 3 MB91460 Series Basic Information6.Pin DefinitionsAV5 502 417 TDT_56 - - - - TE20_0 - C no Tool 4mAAU7 501 420 TDT_55 - - - - TE20_0 - C no

89Chapter 3 MB91460 Series Basic Information6.Pin DefinitionsAR18 439 367 TDT_11 - - - - TE20_0 - C no Tool 4mAAV18 438 366 TDT_10 - - - - TE20_0 - C

90Chapter 3 MB91460 Series Basic Information6.Pin DefinitionsAR29 381 316 EEA_0 - - - - TE10_0 - - no Tool 4mAAT29 380 315 EED_31 - - - - TE20_0 - C n

91Chapter 3 MB91460 Series Basic Information6.Pin DefinitionsAK37 316 263 FLASH_FRSTX - - - - TE10_0 - - no Tool 4mA0.0 637 531 VDD5 - - - - TS02_0 -

92Chapter 3 MB91460 Series Basic Information6.Pin Definitions0.0 659 549 HVDD5 - - - - TS02_0 - - - VDD 5V -B2 686 574 HVSS5 - - - - TS00_0 - - - VSS

93Chapter 3 MB91460 Series Basic Information6.Pin DefinitionsAP20 427 355 VSS3 - - - - TS00_0 - - - VSS -AP24 405 337 VSS3 - - - - TS00_0 - - - VSS -A

viiChapter 34 CAN Controller... 6911. Overview...

94Chapter 3 MB91460 Series Basic Information7.I/O Circuit Type7. I/O Circuit TypeThe table below describes the circuit types which are used on the e

95Chapter 3 MB91460 Series Basic Information7.I/O Circuit TypeTE11_0 - - no Tool 8 mATE20_0 - C no Tool 4 mATE21_0 Dn (ctrl) C no Tool 4 mATE22_0 - C

96Chapter 3 MB91460 Series Basic Information8.Pin State Table8. Pin State TableExplanation of the meaning of words and phrases used in the pin state

97Chapter 3 MB91460 Series Basic Information8.Pin State TableAD35 282 234 P03_7 D7 D7 - -Output Hi-Z,InputenabledOutput Hi-Z,InputenabledState holdOu

98Chapter 3 MB91460 Series Basic Information8.Pin State TableJ37 212 175 P08_7 RDY RDY - -Output Hi-Z,InputenabledOutput Hi-Z,InputenabledState holdO

99Chapter 3 MB91460 Series Basic Information8.Pin State TableD34 165 137 P12_7 DEOP3 DEOP3 - -Output Hi-Z,InputenabledOutput Hi-Z,InputenabledState h

100Chapter 3 MB91460 Series Basic Information8.Pin State TableA25 110 92 P17_7 - PPG7 - -Output Hi-Z,InputenabledOutput Hi-Z,InputenabledState holdOu

101Chapter 3 MB91460 Series Basic Information8.Pin State TableA13 58 47 P22_7 - SCL1 - -Output Hi-Z,InputenabledOutput Hi-Z,InputenabledState holdOut

102Chapter 3 MB91460 Series Basic Information8.Pin State TableA9 36 29 P24_7 - INT7 - SCL3Output Hi-Z,InputenabledOutput Hi-Z,InputenabledState holdO

103Chapter 3 MB91460 Series Basic Information8.Pin State TableB4 5 4 P29_7 - AN7 - -Output Hi-Z,InputenabledOutput Hi-Z,InputenabledState holdOutput:

viii2. Features... 7953. Co

104Chapter 3 MB91460 Series Basic Information8.Pin State TableW1 607 506 P34_7 - SEG15 - -Output Hi-Z,InputenabledOutput Hi-Z,InputenabledState holdO

105Chapter 4 CPU Architecture1.OverviewChapter 4 CPU ArchitectureThis chapter describes the architecture of FR60 family CPU.1. OverviewThe CPUs of t

106Chapter 4 CPU Architecture2.Features2. Features Features of internal architecture• RISC architecture• Base instruction: 1 instruction/1 cycle• 3

107Chapter 4 CPU Architecture3.CPU3. CPUThe CPU realizes the compact implementation of a 32-bit RISC FR architecture.It employs a 5-stage instructio

108Chapter 4 CPU Architecture6.Instruction Overview6. Instruction OverviewThe FR60 family supports logic operation, bit operation and direct address

109Chapter 4 CPU Architecture7.Data Structure7. Data StructureFR60 has two data allocations as follows. Bit OrderingFR60 uses little endian as bit

110Chapter 4 CPU Architecture8.Word Alignment8. Word AlignmentSince instructions and data are accessed by byte, allocated addresses vary by instruct

111Chapter 4 CPU Architecture9.Addressing9. AddressingAddress space is 32-bit linear. MapFigure 9-1 MapFR60’s logical address space is 4GB (232 ad

112Chapter 4 CPU Architecture9.Addressing

113Chapter 5 CPU Registers1.General-purpose RegistersChapter 5 CPU Registers1. General-purpose RegistersRegisters R0 through R15 are general-purpose

ix4. Registers... 9115. Oper

114Chapter 5 CPU Registers2.Dedicated Registers2.1 PC: Program CounterProgram Counter (PC) consists of 32 bits.Figure 2-2 Bit Structure of Program

115Chapter 5 CPU Registers2.Dedicated RegistersThis bit becomes “0” by reset.• [Bit 3] N: Negative flagThis bit indicates the sign when operation res

116Chapter 5 CPU Registers2.Dedicated Registersprogram. ILM: Interrupt Level Mask RegisterFigure 2-6 Register Structure of Interrupt Level Mask Reg

117Chapter 5 CPU Registers2.Dedicated Registers Caution: PS RegisterSince some instructions have already processed PS register in advance, the follo

118Chapter 5 CPU Registers2.Dedicated Registers2.3 TBR: Table-base RegisterTable-base register (TBR) consists of 32 bits.Figure 2-7 Bit Structure o

119Chapter 5 CPU Registers2.Dedicated Registers2.6 USP: User Stack PointerUser Stack Pointer (USP) consists of 32 bits.Figure 2-10 Bit Structure of

120Chapter 5 CPU Registers2.Dedicated Registers2.7 MDH, MDL: Multiply & Divide RegisterMultiply & Divide register (MDH/MDL) consists of 32

121Chapter 6 EIT: Exceptions, Interrupts and Traps1.OverviewChapter 6 EIT: Exceptions, Interrupts and Traps1. OverviewEIT means that some events int

122Chapter 6 EIT: Exceptions, Interrupts and Traps5.EIT Interrupt Level5. EIT Interrupt LevelInterrupt level is between 0 and 31, and controlled wit

123Chapter 6 EIT: Exceptions, Interrupts and Traps7.Multiple EIT Processing7. Multiple EIT ProcessingIf multiple EITs are generated at the same time

x6. Application Note... 973Chapter 51 L

124Chapter 6 EIT: Exceptions, Interrupts and Traps7.Multiple EIT ProcessingFigure 7-1 Multiple EITs ProcessPriority(High) Generation of NMI(Middle)

125Chapter 6 EIT: Exceptions, Interrupts and Traps8.Operation8. OperationIn the following sections, note that source “PC” means instruction address

126Chapter 6 EIT: Exceptions, Interrupts and Traps8.Operation8.2 Operation of INT InstructionINT No. u8 instruction is operated as follows.Branches

127Chapter 6 EIT: Exceptions, Interrupts and Traps8.Operation8.4 Operation of Step Trace TrapIf you set T flag at SCR within PS and enable step trac

128Chapter 6 EIT: Exceptions, Interrupts and Traps9.Caution8.6 Coprocessor Absent TrapIf you execute coprocessor instruction for unmounted coprocess

129Chapter 7 Branch Instruction1.Branch Instruction with Delay SlotChapter 7 Branch InstructionFR60 can instruct the operation with and without delay

130Chapter 7 Branch Instruction3.Actual Example (with Delay Slot)3. Actual Example (with Delay Slot)3.1 JMP:D @Ri / CALL:D @Ri InstructionRi referr

131Chapter 7 Branch Instruction4.Restrictions on Branch Instruction with Delay Slot4. Restrictions on Branch Instruction with Delay Slot4.1 Availab

132Chapter 7 Branch Instruction5.Branch Instruction without Delay Slot5. Branch Instruction without Delay Slot• Branch instruction without delay slo

133Chapter 8 Device State Transition1.OverviewChapter 8 Device State Transition1. Overview MB91460 basically has devices state and flow as shown be

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134Chapter 8 Device State Transition3.State Transition Diagram3. State Transition DiagramThis section describes state transition.Figure 3-1 State T

135Chapter 8 Device State Transition3.State Transition Diagram3.1 RUN (Normal Operation)This is the state where program is executed with all clocks

136Chapter 8 Device State Transition3.State Transition Diagram3.5 Oscillation-stabilization-wait ResetThis is the state where the device is stopped.

137Chapter 8 Device State Transition3.State Transition Diagram

138Chapter 8 Device State Transition3.State Transition Diagram

139Chapter 9 Reset1.OverviewChapter 9 Reset1. OverviewWhen a reset is triggered, the device halts the program and all hardware operation, and then i

140Chapter 9 Reset3.Configuration• A settings initialization reset (INIT) is followed by an operation reset (RST) after the oscillationstabilization t

141Chapter 9 Reset4.Registers4. Registers4.1 RSRR: Reset Cause RegisterStores the cause of the previous reset, and sets the period and activation c

142Chapter 9 Reset4.RegistersIndicates whether a software reset has been triggered by writing to the software reset bit (STCR.SRST).The software rese

143Chapter 9 Reset4.Registers4.2 STCR: Standby Control RegisterThis register is used for software reset control (changing to standby mode, pin contr

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144Chapter 9 Reset4.Registers4.3 MOD: Mode PinsThese pins specify the location of the mode vector and reset vector that are read after the MCU isres

145Chapter 9 Reset4.RegistersInitial value to load into PC.4.6 Device Mode OverviewThe following table gives an overview about supported device mode

146Chapter 9 Reset5.INIT Pin Input (INIT: Settings Initialization Reset)5. INIT Pin Input (INIT: Settings Initialization Reset)5.1 TriggerThe pin i

147Chapter 9 Reset5.INIT Pin Input (INIT: Settings Initialization Reset)5.6 Reset Cancellation SequenceAfter the cancellation (removal) of the setti

148Chapter 9 Reset6.Watchdog Reset (INIT: Settings Initialization Reset)6. Watchdog Reset (INIT: Settings Initialization Reset)6.1 TriggerWriting t

149Chapter 9 Reset7.Software Reset (RST: Operation Initialization Reset)7. Software Reset (RST: Operation Initialization Reset)7.1 TriggerWriting

150Chapter 9 Reset8.Reset Operation Modes8. Reset Operation ModesThe following two different modes can be used for an operation reset (RST):• Normal

151Chapter 9 Reset9.MCU Operation Mode9. MCU Operation ModeAfter release of a reset, the MCU starts operation in the mode specified by the mode pins

152Chapter 9 Reset10.Caution10. Caution• INIT pin inputEnsure that a settings initialization reset (INIT) is applied to this pin when the power is t

153Chapter 9 Reset10.Caution

1Chapter 1 Introduction1.How to Handle the DeviceChapter 1 Introduction1. How to Handle the Device Device Handling InstructionsThis chapter describ

154Chapter 9 Reset10.Caution

155Chapter 10 Standby1.OverviewChapter 10 Standby1. OverviewTwo standby modes (low power consumption modes) are available.• Sleep mode: Stops the

156Chapter 10 Standby3.Configuration3. ConfigurationFigure 3-1 Configuration DiagramFigure 3-2 Register ListState transition control circuitSleep si

157Chapter 10 Standby4.Registers4. Registers4.1 STCR: Standby Control RegisterUsed to control transition to the stop and sleep standby modes, and t

158Chapter 10 Standby4.Registers• Bit0: Main clock oscillation halt4.2 TBCR: Timebase timer control registerThis register controls the timebase timer

159Chapter 10 Standby5.Operation5. Operation5.1 Sleep Mode Entering sleep modeWriting “1” to the sleep mode bit (STCR.SLEEP) changes to sleep mode

160Chapter 10 Standby5.Operation5.2 Stop mode Entering stop modeWriting “1” to the stop mode bit (STCR.STOP) changes to stop mode.The device remain

161Chapter 10 Standby6.Settings6. Settings *:For the setting procedure, refer to the section indicated by the number.*: For the setting procedure, r

162Chapter 10 Standby7.Q&A7.2 How do I change to stop mode?• When operating on the main PLL clock, the operating clock must be set to the main c

163Chapter 10 Standby7.Q&A7.6 How do I recover from stop mode?The following events end stop mode:• The following four interrupts change the devi

2Chapter 1 Introduction1.How to Handle the Device● Caution: during the PLL clock operationEven if oscillator is disconnected or input is stopped whil

164Chapter 10 Standby7.Q&A

165Chapter 10 Standby8.Caution8. Caution• Points to note when changing to sleep modeWhen changing to sleep mode, set the synchronous standby operati

166Chapter 10 Standby8.Caution

167Chapter 11 Memory Controller1.OverviewChapter 11 Memory Controller1. OverviewThis module combines the interfaces to the F-Bus memory resources, F

168Chapter 11 Memory Controller7.Registers• Reset vector address: 0x000ffffc; return 0x00030000 at RAM execution mode (jump to test pro-gram) or retu

169Chapter 11 Memory Controller8.Explanations of Registers8. Explanations of Registers● FLASH Interface Control RegisterFLASH Memory Control and Sta

170Chapter 11 Memory Controller8.Explanations of Registers• BIT[29]: BIRE - Burn-In ROM EnableThe BIRE bit is a reserved bit and should not be used.•

171Chapter 11 Memory Controller8.Explanations of RegistersImportant remark: To maintain data consistency it is strongly recommended to disable the in

172Chapter 11 Memory Controller8.Explanations of Registers• BIT[17]: PF2I - Prefetch 32 bit (2 instructions) onlyWhen switching on 64 bit read mode

173Chapter 11 Memory Controller8.Explanations of Registers• BIT[7]: FLUSH - Flush instruction cache entriesThis bit is set after reset.If the FLUSH b

3Chapter 1 Introduction2.Instruction for Users2. Instruction for Users Clock ControlsBy inputting “L” to INIT, ensure clock oscillation stabilizati

174Chapter 11 Memory Controller8.Explanations of Registers• BIT[4]: PFMC - Prefetch Miss Cache enableThis bit is cleared after reset. The prefetch mi

175Chapter 11 Memory Controller8.Explanations of Registers• BIT[1:0]: SZ[1:0] - Cache size configurationThe cache size is set to ’11’ after reset.The

176Chapter 11 Memory Controller8.Explanations of RegistersWTP controls the wait timing of the FLASH access in case of page hit for Page Mode FLASH. T

177Chapter 11 Memory Controller8.Explanations of RegistersFLASH access cycle waveformFigure 8-1 shows the example of a FLASH access cycle. In the FMW

178Chapter 11 Memory Controller8.Explanations of Registers● FLASH Memory Adddress Check register (FMAC)This register captures the address at the begi

179Chapter 12 Instruction Cache1.General descriptionChapter 12 Instruction CacheThis chapter describes the instruction cache memory included in MB914

180Chapter 12 Instruction Cache2.Main body structureFigure 2-2 Instruction Cache Tag[Bits 31 to 9] Address tagThis area stores the upper 23 bits of

181Chapter 12 Instruction Cache2.Main body structureFLUSHbit is set to "0" when the cache is flushed.)[Bit 1] LRU bit (way 1 only)This bit

182Chapter 12 Instruction Cache2.Main body structure[Bit 7] RAM: RAM ModeSetting this bit to "1" causes the cache to operate in RAM mode. B

183Chapter 12 Instruction Cache2.Main body structureFigure 2-3 I-Cache Address Map

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4Chapter 1 Introduction2.Instruction for Users Caution: PS registerBecause some commands previously proceed PS register, interrupt processing routin

184Chapter 12 Instruction Cache2.Main body structureFigure 2-4 I-Cacheable Area

185Chapter 12 Instruction Cache3.Operating mode conditions3. Operating mode conditions● Cache status in various operating modesThe table below indic

186Chapter 12 Instruction Cache4.Cacheable areas in the instruction cache● Cache Entry UpdateCache entries are updated as shown in the following tabl

187Chapter 12 Instruction Cache5.Settings for handling the I-CacheTo disable the I-Cache, set the ENAB bit to 0.Idi #0x000003e7,r0 // I-Cache control

188Chapter 12 Instruction Cache5.Settings for handling the I-CacheOnly lock information is released; locked instructions are replaced sequentially wi

189Chapter 13 Clock Control1.OverviewChapter 13 Clock Control1. OverviewThe clock control circuit consists of the source oscillator, base clock gene

190Chapter 13 Clock Control3.Configuration• External bus clock (CLKT): F/1, /2, /3, /4, /5, /6, /7, /8, ..., /16The clock used by the external bus exp

191Chapter 13 Clock Control4.Registers4. Registers4.1 CLKR: Clock Source Control RegisterSelects the clock source for the base clock used to run th

192Chapter 13 Clock Control4.Registers• After setting “11B” (subclock), insert one or more NOP instructions.• Selecting the subclock as the clock sou

193Chapter 13 Clock Control4.Registers4.2 DIV0R: Clock Division Setting Register 0Sets the division ratio for the clocks used for internal device op

5Chapter 1 Introduction2.Instruction for Users Caution: writing to registers which include a status flagWriting to a register including a status fla

194Chapter 13 Clock Control4.Registers• Sets the clock division ratio for the clock used by the peripheral circuits and peripheral bus (CLKP).The 16

195Chapter 13 Clock Control4.Registers4.3 DIV1R: Clock Division Setting Register 1Sets the division ratio for the clocks used for internal device op

196Chapter 13 Clock Control4.Registers4.4 CSCFG: Clock Source Configuration RegisterThis register controls the main clock oscillation in subclock mod

197Chapter 13 Clock Control4.Registers-1-- Subclock Calibration is sourced by RC Oscillation0--- LCD Controller is sourced by Sub Oscillation1--- LCD

198Chapter 13 Clock Control4.Registers4.5 OSCCR: Oscillation Control RegisterThis register controls the main clock oscillation in subclock mode• OSC

199Chapter 13 Clock Control5.Operation5. OperationThis section describes how to setup and switch between clocks.5.1 Clock Setup Sequence (Example)5

200Chapter 13 Clock Control5.Operation5.3 Notes Main PLL controlAfter initialization, the main PLL oscillation is halted. While halted, the output

201Chapter 13 Clock Control6.Settings6. Settings*: For the setting procedure, refer to the section indicated by the number.*: For the setting proced

202Chapter 13 Clock Control7.Q & A7. Q & A7.1 How do I enable or disable clock operation?• There is no operation enable bit for the main cl

203Chapter 13 Clock Control7.Q & A7.4 How do I set the operation clock division ratios?• CPU clock settingThe CPU clock setting is set using the

6Chapter 1 Introduction3.Caution: debug-related matters3. Caution: debug-related matters Stepwise execution of RETI commandUnder the circumstances

204Chapter 13 Clock Control7.Q & A7.5 How do I halt the main clock in sub clock mode?Set using the “halt main clock oscillation in subclock mode

205Chapter 13 Clock Control8.Caution8. Caution• Operation is not guaranteed if the clock source selection, main PLL multiplier setting, and division

206Chapter 13 Clock Control8.Caution

207Chapter 14 PLL Interface1.OverviewChapter 14 PLL Interface1. Overview• This blockdiagram (simplified) shows the integration of the PLL and the PL

208Chapter 14 PLL Interface4.Registers4. Registers4.1 PLL Control RegistersControls the PLL multiplier ratio (divide-by-M and divide-by-N) and the

209Chapter 14 PLL Interface4.Registers(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)• Bit7-6: Reserved bits.The

210Chapter 14 PLL Interface4.Registers• PLLMULG: Address 048Fh (Access: Byte, Halfword, Word)(See “Meaning of Bit Attribute Symbols (Page No.10)” for

211Chapter 14 PLL Interface4.Registers• While switching from clock source PLL to clock source oscillator this flag is set when the divide-by-Gcounter

212Chapter 14 PLL Interface5.Recommended Settings5. Recommended Settings• Important remark: Not all settings which are shown in this table are availa

213Chapter 14 PLL Interface6.Clock Auto Gear Up/Down6. Clock Auto Gear Up/DownTo avoid voltage drops and surges when switching the clock source from

7Chapter 1 Introduction4.How to Use This Document4. How to Use This Document Main terminology: This table shows main terminology used for FR60.Term

214Chapter 14 PLL Interface6.Clock Auto Gear Up/Downthis equals to (resolved closed arithmetic series of the first sum term):with i = G ; j = G - M ;

215Chapter 14 PLL Interface7.Caution7. CautionWhen using the clock auto-gear function it is strongly recommended to make use of the gear up and gear

216Chapter 14 PLL Interface7.Caution

217Chapter 15 CAN Clock Prescaler1.OverviewChapter 15 CAN Clock Prescaler1. Overview• This blockdiagram (simplified) shows the integration of the CA

218Chapter 15 CAN Clock Prescaler3.Registers3. Registers3.1 CAN Clock Control RegisterControls the CAN clock source, the clock division ratio and t

219Chapter 15 CAN Clock Prescaler3.Registers(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)• Bit7-6: Reserved bi

220Chapter 15 CAN Clock Prescaler3.Registers

221Chapter 16 Clock Supervisor1.Overview Clock SupervisorChapter 16 Clock SupervisorThis section gives an overview of the Clock Supervisor. Purpose o

222Chapter 16 Clock Supervisor2.Clock Supervisor Register2. Clock Supervisor RegisterThis section lists the Clock Supervisor Control Register and de

223Chapter 16 Clock Supervisor2.Clock Supervisor RegisterTable 2-1 describes the function of each bit of the Clock Supervisor Control Register (CSVCR

8Chapter 1 Introduction4.How to Use This Document Access size and address positionThere are three kinds of accesses such as Byte access, Half-word

224Chapter 16 Clock Supervisor3.Block Diagram Clock Supervisor3. Block Diagram Clock SupervisorThis section presents a block diagram of the Clock Su

225Chapter 16 Clock Supervisor4.Operation Modes4. Operation ModesThis section describes all operation modes of the Clock Supervisor. Operation mode

226Chapter 16 Clock Supervisor4.Operation ModesFigure 4-1 Timing Diagram: Initial settings, main clock missing during power-on resetPONRMCLKSCLKRC_C

227Chapter 16 Clock Supervisor4.Operation ModesFigure 4-2 Timing Diagram: Initial settings, main clock missing during ’oscillation stabilisation wai

228Chapter 16 Clock Supervisor4.Operation ModesFigure 4-3 Timing Diagram: Initial settings, main clock missing after ’oscillation stabilisation wait

229Chapter 16 Clock Supervisor4.Operation ModesFigure 4-4 Timing Diagram: Initial settings, sub-clock missing before timeoutPONRMCLKSCLKRC_CLKOSC_ST

230Chapter 16 Clock Supervisor4.Operation ModesFigure 4-5 Timing Diagram: Initial settings, sub-clock missing after timeoutPONRMCLKSCLKRC_CLKOSC_STA

231Chapter 16 Clock Supervisor4.Operation Modes Disabling the RC-oscillator and the clock supervisorsThe initial point of this scenario is that the

232Chapter 16 Clock Supervisor4.Operation Modes Re-enabling the RC-oscillator and the clock supervisorsThe initial point of this scenario is that th

233Chapter 16 Clock Supervisor4.Operation Modes Sub-clock modesThe main clock supervisor is automatically disabled in sub-clock modes. The enable bi

9Chapter 1 Introduction4.How to Use This Document About access size and bit positionWhen access size changes, bit position changes.• In the case tha

234Chapter 16 Clock Supervisor4.Operation ModesFigure 4-9 Timing Diagram: Sub-clock missing in main clock mode, SRST=1PONRMCLKSCLKRC_CLKOSC_STABMSVE

235Chapter 16 Clock Supervisor4.Operation ModesFigure 4-10 Timing Diagram: Waking up from sub-clock modePONRMCLKSCLKRC_CLKOSC_STABMSVEMSENSSVESSENMC

236Chapter 16 Clock Supervisor4.Operation Modes Stop modeIf RC-oscillator, main clock and sub-clock supervisors are enabled, they will be automatica

237Chapter 16 Clock Supervisor4.Operation Modes Operation with single clock deviceIn a single clock device the sub-clock supervisor can provide the

238Chapter 16 Clock Supervisor4.Operation Modes Check if reset was asserted by the Clock SupervisorTo find out whether the Clock Supervisor has asse

239Chapter 17 Clock Modulator1.OverviewChapter 17 Clock ModulatorThis chapter provides an overview of the Clock Modulator and its features. It descri

240Chapter 17 Clock Modulator2.Clock Modulator Registers2. Clock Modulator RegistersThis section lists the clock modulator registers and describes t

241Chapter 17 Clock Modulator2.Clock Modulator Registers● Clock Modulator Control Register (CMCR)The Control Register (CMCR) has the following functi

242Chapter 17 Clock Modulator2.Clock Modulator Registers● Clock modulator control register contentsTable 2-1 Function of each bit of the clock modul

243Chapter 17 Clock Modulator2.Clock Modulator RegistersIn the Table below the modulator states are summarized:bit 1 FMOD:Frequencymodulationenable b

10Chapter 1 Introduction4.How to Use This Document Meaning of Bit Attribute Symbols R : Readable W : Writable RM : Reading operation during read/

244Chapter 17 Clock Modulator2.Clock Modulator Registers● Clock Modulation Parameter Register (CMPR)The Modulation Parameter Register (CMPR) determin

245Chapter 17 Clock Modulator2.Clock Modulator Registersbit 13 to 0 MP13 to 0:ModulationParameter bitsDepending on the PLL frequency the following mo

246Chapter 17 Clock Modulator2.Clock Modulator RegistersNote: NOT ALL SETTINGS ARE ALLOWED ON EVERY DEVICE!Please consider the actual maximal allowed

247Chapter 17 Clock Modulator3.Application NoteThe table below shows the recommended setting for several MCU clocks and modulation parameters:Please

248Chapter 17 Clock Modulator3.Application Noterecommended.● Recommended settingsThe following table lists some example conditions for PLL clock and

249Chapter 18 Timebase Counter1.OverviewChapter 18 Timebase Counter1. OverviewThe timebase counter is a 26-bit up-counter that counts the subclock o

250Chapter 18 Timebase Counter3.Configuration Events that invoke an oscillation stabilization wait using other than the timebase counter● Wait time a

251Chapter 18 Timebase Counter4.Registers4. Registers4.1 STCR: Standby Control RegisterControls transition to standby modes, pin states during stop

252Chapter 18 Timebase Counter4.Registers4.2 CLKR: Clock Source Control RegisterSelects the clock source for the base clock used to run the MCU and

253Chapter 18 Timebase Counter5.Operation5. OperationThis section describes the events that trigger an oscillation stabilization wait and the operat

11Chapter 2 MB91460 Rev.A/Rev.B Overview1.OverviewChapter 2 MB91460 Rev.A/Rev.B Overview1. OverviewMB91460 is a series of standard microcontrollers

254Chapter 18 Timebase Counter5.Operation5.2 Watchdog Reset (The specified oscillation stabilization wait time is generatedautomatically)If a watchdo

255Chapter 18 Timebase Counter5.Operation Watchdog reset when main clock operatingAlthough no oscillation stabilization wait is required in this cas

256Chapter 18 Timebase Counter5.Operation When changing to stop mode without halting the clock oscillation circuit (main PLL/main/sub):Although no o

257Chapter 18 Timebase Counter5.Operation5.7 Types of Oscillation Stabilization Wait Timebase counterAutomatically provides a count for the oscilla

258Chapter 18 Timebase Counter5.Operation5.8 Whether or not a Stabilization Wait is Required for Each State TransitionSee figure below.

259Chapter 18 Timebase Counter6.Settings6. Settings*: For the setting procedure, refer to the section indicated by the number.• Settings required to

260Chapter 18 Timebase Counter7.Q&A7. Q&A7.1 How do I setup the oscillation stabilization wait time that is generated automatically?Use the

261Chapter 18 Timebase Counter7.Q&A7.2 How do I set the oscillation stabilization wait time without generating itautomatically?The settings desc

262Chapter 18 Timebase Counter8.Caution8. Caution• Clock sourceIf the clock selected as the clock source is not stable, an oscillation stabilization

263Chapter 19 Timebase Timer1.OverviewChapter 19 Timebase Timer1. OverviewThe timebase timer is a selector that uses the output from a 26-bit timeba

12Chapter 2 MB91460 Rev.A/Rev.B Overview2.Features• 4 words (16 bytes) per set• Variable capacity (4/2/1 kB)• Lock function enabling programs to be r

264Chapter 19 Timebase Timer3.Configuration3. ConfigurationFigure 3-1 ConfigurationFigure 3-2 List of Registers10TimebaseTimer interrupt(#46)Timebas

265Chapter 19 Timebase Timer4.Register4. Register4.1 TBCR: Timebase Timer Control RegisterThis register is used to set timebase timer interrupt co

266Chapter 19 Timebase Timer4.Register• Bit1: Enabling the synchronous reset operation• Ordinary operation reset: Immediately resets the operation in

267Chapter 19 Timebase Timer5.Operation5. OperationTimebase timer operation is described.5.1 Timebase Timer Interrupt Example (Main PLL Lock Wait)(

268Chapter 19 Timebase Timer6.Setting6. Setting*: Refer to the number for more information on the setting method.*: Refer to the number for more inf

269Chapter 19 Timebase Timer7.Q & A7. Q & A7.1 What are the types of interval time used in the timebase timer (and the timebasecounter used

270Chapter 19 Timebase Timer7.Q & A7.7 What are the interrupt types?One type of interrupt is available, and an interrupt is generated when the

271Chapter 19 Timebase Timer8.Caution8. Caution• The main PLL needs the PLL lock wait time after operation enable and after modifying the rate of mu

272Chapter 19 Timebase Timer8.Caution

273Chapter 20 Software Watchdog Timer1.OverviewChapter 20 Software Watchdog Timer1. OverviewThe software watchdog timer consists of a selector that

13Chapter 2 MB91460 Rev.A/Rev.B Overview2.Features• 3 types of transfer sources (external pins/internal peripherals/and software)• Up to 128 selectab

274Chapter 20 Software Watchdog Timer3.Configuration3. ConfigurationFigure 3-1 Configuration DiagramFigure 3-2 List of RegistersTimebase counterBase

275Chapter 20 Software Watchdog Timer4.Register4. Register4.1 RSRR: Watchdog Timer Control RegisterThis register is used to set watchdog timer peri

276Chapter 20 Software Watchdog Timer4.RegisterThe software reset occurred flag (SRST) is cleared to “0” after reading.• Bit2: Low voltage reset occu

277Chapter 20 Software Watchdog Timer4.Register4.2 WPR: Watchdog Reset Generation Postponement RegisterThis register is used to postpone the generat

278Chapter 20 Software Watchdog Timer5.Operation5. Operation This section describes the watchdog operation.5.1 Watchdog (Detecting Runaway)(1) Sett

279Chapter 20 Software Watchdog Timer5.Operation5.2 Starting the Watchdog Timer and Setting the Watchdog Timer PeriodThe watchdog timer starts once

280Chapter 20 Software Watchdog Timer6.Setting6. Setting*: Refer to the number for more information on the setting method.*: Refer to the number for

281Chapter 20 Software Watchdog Timer7.Q & A7. Q & A7.1 What are the types of watchdog interval time and how are they selected?There are f

282Chapter 20 Software Watchdog Timer8.Caution8. Caution• Although the watchdog interval time corresponds to the one twice as long as the watchdog 1

283Chapter 21 Hardware Watchdog Timer1.OverviewChapter 21 Hardware Watchdog Timer1. OverviewThe hardware watchdog timer (R/C oscillation based) prov

FR6032-BIT MICROCONTROLLERMB91460 SeriesUser’s Manual

14Chapter 2 MB91460 Rev.A/Rev.B Overview2.Features2.10 Peripheral Function• General-purpose port : Up to 288• N channel open drain port out of above

284Chapter 21 Hardware Watchdog Timer2.Configuration2. ConfigurationHardware watchdog timer consists of two sub-blocks:• Watchdog timer• Timer contro

285Chapter 21 Hardware Watchdog Timer3.Register3. Register3.1 Hardware watchdog timer control and status registerHardware watchdog timer control st

286Chapter 21 Hardware Watchdog Timer3.Register3.2 Hardware watchdog timer duration registerHardware watchdog timer duration register (elongation of

287Chapter 21 Hardware Watchdog Timer4.Functions4. FunctionsIf the watchdog timer is not cleared periodically, a setting initialization reset (INIT)

288Chapter 21 Hardware Watchdog Timer5.Caution5. Caution● Software disabling is not possibleThe watchdog timer starts counting immediately after res

289Chapter 22 Main Oscillation Stabilisation Timer1.OverviewChapter 22 Main Oscillation Stabilisation Timer1. OverviewThe main clock oscillation sta

290Chapter 22 Main Oscillation Stabilisation Timer3.Configuration3. ConfigurationFigure 3-1 Configuration DiagramFigure 3-2 List of RegistersNote: R

291Chapter 22 Main Oscillation Stabilisation Timer4.Register4. Register4.1 OSCRH: Control Register for the Main Clock Oscillation Stability Wait T

292Chapter 22 Main Oscillation Stabilisation Timer5.Operation5. Operation This section describes the main clock oscillation stability wait timer ope

293Chapter 22 Main Oscillation Stabilisation Timer5.Operation5.2 Interval Interrupt(1) Selects the interval time (WS[1:0]). (In this example, 217/F

15Chapter 2 MB91460 Rev.A/Rev.B Overview2.Features• 16-bit reload counter• Includes clock prescaler (fRES/21, fRES/23, fRES/25, fRES/26, fRES/27)• Fr

294Chapter 22 Main Oscillation Stabilisation Timer6.Setting6. Setting*: Refer to the number for more information on the setting method.*: Refer to t

295Chapter 22 Main Oscillation Stabilisation Timer7.Q & A7. Q & A7.1 What are the types of interval time (wait time) and how are they selec

296Chapter 22 Main Oscillation Stabilisation Timer7.Q & A7.6 What are the types of interrupt?There is one type of interrupt called the main cloc

297Chapter 22 Main Oscillation Stabilisation Timer8.Caution8. Caution• To wait until the main clock oscillation stability is attained while the subc

298Chapter 22 Main Oscillation Stabilisation Timer8.Caution

299Chapter 23 Sub Oscillation Stabilisation Timer1.OverviewChapter 23 Sub Oscillation Stabilisation Timer1. OverviewThe sub oscillation stabilisatio

300Chapter 23 Sub Oscillation Stabilisation Timer3.Configuration3. ConfigurationFigure 3-1 Configuration DiagramFigure 3-2 List of RegistersNote: Fo

301Chapter 23 Sub Oscillation Stabilisation Timer4.Register4. Register4.1 WPCRH: Sub oscillation stabilisation timer Control RegisterThis register

302Chapter 23 Sub Oscillation Stabilisation Timer4.Register watchdog reset), but the operation initialization reset (Software reset) holds the cu

303Chapter 23 Sub Oscillation Stabilisation Timer5.Operation5. Operation5.1 Subclock Oscillation Stability Wait InterruptFigure 5-1 Reference(1) S

16Chapter 2 MB91460 Rev.A/Rev.B Overview2.Features• LIN-USART (LIN=Local Interconnect Network) : 16 channels• Full-duplex double buffer system (4 ch

304Chapter 23 Sub Oscillation Stabilisation Timer5.Operation5.2 Interval Interrupt (Clock Interrupt)(1) Selects the interval time. (WS[1:0]) (In thi

305Chapter 23 Sub Oscillation Stabilisation Timer5.Operation5.3 Returning from the Stop Mode due to Interval Operation (Clock Interrupt)(1) The sub

306Chapter 23 Sub Oscillation Stabilisation Timer6.Setting6. Setting*: Refer to the number for more information on the setting method.*: Refer to th

307Chapter 23 Sub Oscillation Stabilisation Timer7.Q & A7. Q & A7.1 What are the types of interval time (wait time) and how are they selec

308Chapter 23 Sub Oscillation Stabilisation Timer7.Q & A7.6 How is the interrupt enabled?The interrupt request enable and the interrupt request

309Chapter 23 Sub Oscillation Stabilisation Timer8.Caution8. Caution• If the setting request (WIF=“1”) of the timer interrupt request flag and the w

310Chapter 23 Sub Oscillation Stabilisation Timer8.Caution

311Chapter 24 Interrupt Control1.OverviewChapter 24 Interrupt Control1. OverviewInterrupt control manages interrupt reception and arbitration.2. Fe

312Chapter 24 Interrupt Control3.Configuration3. ConfigurationFigure 3-1 Configuration DiagramFigure 3-2 Configuration DiagramInterrupt priority judg

313Chapter 24 Interrupt Control4.Registers4. Registers4.1 ICR: Interrupt Control RegisterThe register that specifies the interrupt level of an inte

17Chapter 2 MB91460 Rev.A/Rev.B Overview2.Featuresthe range of 1 to 1.5 cycles of the resource clock (CLKP)• PFM (pulse frequency modulator) : 16 bit

314Chapter 24 Interrupt Control4.RegistersICR29#74 I2C 0 / I2C 2: Address 045DH(Access: Byte)#75 I2C 1 / I2C 3ICR30#76 USART (LIN) 8 RX: Address 045E

315Chapter 24 Interrupt Control4.Registers(*1) : Used by REALOS(*2): ICR23 and ICR47 can be exchanged by setting the REALOS compatibility bit (addr 0

316Chapter 24 Interrupt Control4.RegistersICR (Interrupt Control Register) is a register in the interrupt controller, and it specifies the interrupt

317Chapter 24 Interrupt Control4.Registers4.2 Interrupt VectorInterrupt vector that corresponds to a vector number (#) with TBR register set to 0FFC

318Chapter 24 Interrupt Control5.Operation5. OperationThe following section explains priority determination operation of interrupt control. Priorit

319Chapter 24 Interrupt Control6.Setting6. Setting*: For the setting procedure, refer to the section indicated by the number.7. Q & A7.1 How c

320Chapter 24 Interrupt Control8.Caution7.4 How can I set an I flag?8. CautionInterrupt request flags are not cleared automatically. Make sure to cl

321Chapter 25 External Interrupt1.OverviewChapter 25 External Interrupt1. OverviewExternal interrupt detects a signal input to an external interrupt

322Chapter 25 External Interrupt3.Configuration3. ConfigurationFigure 3-1 Configuration DiagramExternal interrupts 0 - 7LB0, LA0 LB1, LA1 LB2, LA

323Chapter 25 External Interrupt3.ConfigurationFigure 3-2 Configuration DiagramFigure 3-3 Register ListExternal interrupts 8 - 15LB8, LA8 LB9, LA9

18Chapter 2 MB91460 Rev.A/Rev.B Overview2.Features• Prescaler value for 32 kHz is 001FFFH• Clock monitor (clock output function): 1 channel• Clock su

324Chapter 25 External Interrupt3.ConfigurationFigure 3-4 Register ListNote: See “Chapter 24 Interrupt Control (Page No.311)” about ICR register and

325Chapter 25 External Interrupt4.Registers4. Registers4.1 ELVR: Interrupt Request Level RegisterThe register that selects request detection of ext

326Chapter 25 External Interrupt4.Registers4.2 EIRR: Interrupt Request RegisterStatus bit of a request of an external interrupt.• EIRR0 (INT0-INT7):

327Chapter 25 External Interrupt5.Operation5. Operation(1) External interrupt signal (INT) input(2) Detect interrupt signals (level/edge).(3) Valid

328Chapter 25 External Interrupt6.Setting6. SettingNote: For the setting procedure, refer to the section indicated by the number.7. Q & A7.1 W

329Chapter 25 External Interrupt7.Q & A7.3 What interrupt registers are used?Setting of interrupt vectors of external interrupts, and interrupt

330Chapter 25 External Interrupt7.Q & A7.5 How do I enable, disable, and clear interrupts?Enable flag for interrupt requests, interrupt request

331Chapter 25 External Interrupt8.Caution8. Caution• When the request input is a level (LAn, LBn = “00” or “01”) and when the INT pin input is the s

332Chapter 25 External Interrupt8.Caution

333Chapter 26 DMA Controller1.Overview of the DMA Controller (DMAC)Chapter 26 DMA Controller1. Overview of the DMA Controller (DMAC)The DMA controll

19Chapter 2 MB91460 Rev.A/Rev.B Overview3.MB91460 Series Product Lineup3. MB91460 Series Product LineupFeature MB91V460 Rev.A MB91V460 Rev.B MB91F46

334Chapter 26 DMA Controller1.Overview of the DMA Controller (DMAC) Block DiagramFigure 1-1"Block Diagram of the DMA Controller (DMAC)" is

335Chapter 26 DMA Controller2.DMA Controller (DMAC) Registers2. DMA Controller (DMAC) RegistersThis section describes the configuration and function

336Chapter 26 DMA Controller2.DMA Controller (DMAC) RegistersIf the bit is set while DMA transfer start is disabled (when DMAE of DMACR=0, or DENB of

337Chapter 26 DMA Controller2.DMA Controller (DMAC) Registers[Bit 30] PAUS (PAUSe)*: Temporary stop instructionThis bit temporarily stops DMA transfe

338Chapter 26 DMA Controller2.DMA Controller (DMAC) Registers[Bits 28 to 24] IS4 to 0 (Input Select)*: Transfer source selectionThese bits select the

339Chapter 26 DMA Controller2.DMA Controller (DMAC) RegistersNotes:• If DMA start resulting from an interrupt from a peripheral function is set (IS=1

340Chapter 26 DMA Controller2.DMA Controller (DMAC) Registers10110 0010 38 Reload Timer 6 -10111 0010 39 Reload Timer 7 -11000 0010 40 Free Run Timer

341Chapter 26 DMA Controller2.DMA Controller (DMAC) Registers10110 0100 70 USART (LIN) 11 RX available10111 0100 71 USART (LIN) 11 TX -11000 0100 72

342Chapter 26 DMA Controller2.DMA Controller (DMAC) Registers• When reset: IS4-0 is initialized to 00000B.• When reset: EIS3-0 is initialized to 0000

343Chapter 26 DMA Controller2.DMA Controller (DMAC) Registerscompleted.When DMA transfer is started, data in this register is stored in the counter b

20Chapter 2 MB91460 Rev.A/Rev.B Overview3.MB91460 Series Product LineupMB91V460 Rev.B : This series is presently being specified and not available ye

344Chapter 26 DMA Controller2.DMA Controller (DMAC) Registersmemory address.• When reset: Initialized to 00B.• These bits are readable and writable.T

345Chapter 26 DMA Controller2.DMA Controller (DMAC) Registers[Bits 29, 28] MOD (MODe)*: Transfer mode settingThese bits are the transfer mode setting

346Chapter 26 DMA Controller2.DMA Controller (DMAC) Registers[Bit 25] SADM (Source-ADdr. Count-Mode select)*: Transfer source address count mode spec

347Chapter 26 DMA Controller2.DMA Controller (DMAC) Registers[Bit 23] DTCR (DTC-reg. Reload)*: Transfer count register reload specificationThis bit c

348Chapter 26 DMA Controller2.DMA Controller (DMAC) Registers[Bit 21] DADR (Dest.-ADdr.-reg. Reload)*: Transfer destination address register reload s

349Chapter 26 DMA Controller2.DMA Controller (DMAC) Registers[Bits 18 to 16] DSS2 to 0 (DMA Stop Status)*: Transfer stop source indicationThese bits

350Chapter 26 DMA Controller2.DMA Controller (DMAC) Registers[Bits 7 to 0] DASZ (Des Addr count SiZe)*: Transfer destination address count size speci

351Chapter 26 DMA Controller2.DMA Controller (DMAC) Registers[Bits 31 to 0] DMADA (DMA Destination Addr)*: Transfer destination address settingThese

352Chapter 26 DMA Controller2.DMA Controller (DMAC) RegistersDMA operation can be forced to stop by writing 0 to this bit. However, be sure to force

353Chapter 26 DMA Controller2.DMA Controller (DMAC) Registers Pin Function of the DACK, and DEOP, and DREQ pinsTo use the DACK, DEOP, or DREQ pins f

21Chapter 2 MB91460 Rev.A/Rev.B Overview4.Block Diagram4. Block DiagramThe following illustration shows the block diagram of MB91460 series.Figure 4

354Chapter 26 DMA Controller3.DMA Controller (DMAC) Operation3. DMA Controller (DMAC) OperationA DMA controller (DMAC) is built into all FR family d

355Chapter 26 DMA Controller3.DMA Controller (DMAC) Operation● Fly-by transfer (I/O --> memory)The DMA controller operates using a write operation

356Chapter 26 DMA Controller3.DMA Controller (DMAC) Operation• End of the specified transfer count (DMACA:BLK[3:0] x DMACA:DTC[15:0]) => Normal en

357Chapter 26 DMA Controller3.DMA Controller (DMAC) Operationalways be caused.If a software request occurs together with a start (transfer enable) re

358Chapter 26 DMA Controller3.DMA Controller (DMAC) OperationFigure 3-1 Example of burst transfer for a start on an external pin rising edge, number

359Chapter 26 DMA Controller3.DMA Controller (DMAC) OperationNote:For a demand transfer, be sure to set an external area address for the transfer sou

360Chapter 26 DMA Controller3.DMA Controller (DMAC) Operation• If a transfer request for another channel with a higher priority is received during tr

361Chapter 26 DMA Controller3.DMA Controller (DMAC) Operation● Transfer count register reloadingAfter transfer is performed the specified number of t

362Chapter 26 DMA Controller3.DMA Controller (DMAC) Operation Features of the Address RegisterThis register has the maximum 32-bit length. With 32-b

363Chapter 26 DMA Controller3.DMA Controller (DMAC) Operation Transfer Count ControlSet the transfer count value in the transfer count register (DTC

22Chapter 2 MB91460 Rev.A/Rev.B Overview4.Block Diagram

364Chapter 26 DMA Controller3.DMA Controller (DMAC) OperationNote:• Since the register has only four bits, this function cannot be used for multiple

365Chapter 26 DMA Controller3.DMA Controller (DMAC) OperationIf edge detection is selected for the external pin start source and a transfer request i

366Chapter 26 DMA Controller3.DMA Controller (DMAC) Operation● Disabling all channelsIf the operation of all channels is disabled with the DMA operat

367Chapter 26 DMA Controller3.DMA Controller (DMAC) Operation Occurrence of an Address ErrorIf inappropriate addressing, as shown below in parenthes

368Chapter 26 DMA Controller3.DMA Controller (DMAC) Operation3.11 Channel Selection and ControlUp to five channels can be simultaneously set as tran

369Chapter 26 DMA Controller3.DMA Controller (DMAC) Operation Channel GroupThe order of priority is set as shown in the following table.3.12 Supple

370Chapter 26 DMA Controller3.DMA Controller (DMAC) OperationFigure 3-7 Negate timing example of the DREQ pin input for 2-cycle external transfer --

371Chapter 26 DMA Controller3.DMA Controller (DMAC) OperationEven if DREQ is reasserted earlier, it is ignored because the transfer has not been comp

372Chapter 26 DMA Controller3.DMA Controller (DMAC) Operation AC Characteristics of DMACDREQ pin input, DACK pin output, and DEOP pin output are pro

373Chapter 26 DMA Controller4.Operation Flowcharts4. Operation FlowchartsThis section contains operation flowcharts for the following transfer modes

23Chapter 3 MB91460 Series Basic Information1.Memory MapChapter 3 MB91460 Series Basic InformationThis chapter describes MB91460 series basic informa

374Chapter 26 DMA Controller4.Operation FlowchartsFigure 4-2 Operation Flowchart for Burst Transfer Demand TransferFigure 4-3"Operation Flowch

375Chapter 26 DMA Controller4.Operation FlowchartsFigure 4-3 Operation Flowchart for Demand TransferLoad the initial address,transfer count, andnumb

376Chapter 26 DMA Controller5.Data Bus5. Data BusThis section shows the flow of data during 2-cycle transfer and fly-by transfer. Flow of Data Duri

377Chapter 26 DMA Controller5.Data Bus Flow of Data During Fly-By TransferFigure 5-2"Examples of Fly-By Transfer" shows examples of two ty

378Chapter 26 DMA Controller5.Data BusFigure 5-2 Examples of Fly-By TransfermemoryMemory read by RD or CSnI/O write by RD or DACKmemoryMemory write

379Chapter 26 DMA Controller6.DMA External Interface6. DMA External InterfaceThis section provides operation timing charts for the DMA external inte

380Chapter 26 DMA Controller6.DMA External Interface Timing of Demand TransferFor demand transfer, set the DMA start source to level detection. Alth

381Chapter 26 DMA Controller6.DMA External InterfaceFigure 6-3 Timing Chart in 2-Cycle Transfer Mode● Fly-by transfer modeFigure 6-4"Timing Cha

382Chapter 26 DMA Controller6.DMA External Interface

383Chapter 27 Delayed Interrupt1.OverviewChapter 27 Delayed Interrupt1. OverviewThe delayed interrupt, or the delayed interrupt module is used to ge

-i©2004 FUJITSU LIMITED Printed in Japan• The contents of this document are subject to change without notice.Customers are advised to consult with FUJ

24Chapter 3 MB91460 Series Basic Information2.I/O Map2. I/O MapThis section shows the association between memory space and each register of peripher

384Chapter 27 Delayed Interrupt4.Register4. Register4.1 DICR:Delayed Interrupt Control RegisterThis register controls to generate/clear the delayed

385Chapter 27 Delayed Interrupt6.Setting6. SettingTable Setting required for the delayed interrupt generation/clear*: Refer to the number for the se

386Chapter 27 Delayed Interrupt8.Caution

387Chapter 28 Bit Search1.OverviewChapter 28 Bit Search1. Overview The bit search module is used to detect 0, 1 or changing position for data writte

388Chapter 28 Bit Search3.Configuration3. ConfigurationFigure 3-1 Configuration DiagramFigure 3-2 List of RegistersBSRRBSD0/ BSD1/ BSDC0-/1-/Changin

389Chapter 28 Bit Search4.Register4. Register4.1 BSD0: 0 Detection Register / BSD1:1 Detection Register / BSDC: Changing positionDetection Data Reg

390Chapter 28 Bit Search4.Register4.2 BSRR: Detection Result RegisterThis register is used to read a bit search result.• BSRR: Address 03FCH (Access

391Chapter 28 Bit Search5.Operation5. Operation5.1 Zero detection(1) Bit position from MSB(2) Written data (Starts to search once data is written.)

392Chapter 28 Bit Search5.Operation5.3 Changing Position Detection(1) Bit position from MSB(2) Written data (Detection starts once data is written.)

393Chapter 28 Bit Search6.Setting6. Setting*: For detailed description contents, refer to the reference destination number.*: For detailed descripti

25Chapter 3 MB91460 Series Basic Information2.I/O MapTable 2-1 I/O MapAddressRegisterBlock+0 +1 +2 +3000000HPDR00 [R/W]XXXXXXXXPDR01 [R/W]XXXXXXXXPD

394Chapter 28 Bit Search7.Q & A7. Q & A7.1 How is data written?Writes data with the detection data registers (BSD0, BSD1, BSDC).7.2 How is

395Chapter 28 Bit Search8.Caution8. CautionThe following are the remarks on using the bit search module.• The macros are for REALOS(OS), and the use

396Chapter 28 Bit Search8.Caution

397Chapter 29 MPU / EDSU1.OverviewChapter 29 MPU / EDSU1. OverviewMemory Protection Unit (MPU) and Embedded Debug Support Unit (EDSU) for MB91460 se

398Chapter 29 MPU / EDSU2.Features2. FeaturesOne Comparator Group offers up to 4 Breakpoints. One Group consists of two full-featured range comparat

399Chapter 29 MPU / EDSU3.Break Functions3. Break Functions3.1 Instruction address breakThe instruction address point break is the most basic break

400Chapter 29 MPU / EDSU3.Break FunctionsBreak occurs at 0x02345200 to 0x02345300,orat 0x12345200 to 0x12345300,orat 0x22345200 to 0x22345300, etc.Th

401Chapter 29 MPU / EDSU3.Break FunctionsExample: CTC 01 Type: Operand Address BreakEP0 1 Enable break point on BAD0EP1 1 Enable break point on BAD1E

402Chapter 29 MPU / EDSU3.Break FunctionsIn Operand address break mode the Operand Address, causing the break is captured in the BOAC register. Addi-

403Chapter 29 MPU / EDSU3.Break Functions2) The EDSU data break does not always occur immediately after completion of execution of the instruction ca

26Chapter 3 MB91460 Series Basic Information2.I/O Map000048HSCR01 [R/W,W]00000000SMR01 [R/W,W]00000000SSR01 [R/W,R]00001000RDR01/TDR01[R/W]00000000US

404Chapter 29 MPU / EDSU3.Break FunctionsOn break both BD0 and BD2, respective BD1 and BD3 are set. They have to be reset by software in the operandb

405Chapter 29 MPU / EDSU3.Break FunctionsPermissions can be set for the comparator channel CMP1 and CMP0 separately, indicated by the symbol index.At

406Chapter 29 MPU / EDSU3.Break FunctionsBreak factors and corresponding interrupt numbers and vectors:Table 3-8 Interrupt numbers and vectors of br

407Chapter 29 MPU / EDSU4.Registers4. Registers4.1 List of EDSU RegistersTable 4-1 EDSU Registers SummaryAddress Register Block+0 +1 +2 +3F000HBCT

408Chapter 29 MPU / EDSU4.RegistersF080HBAD0 [R/W]XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXXEDSUF084HBAD1 [R/W]XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXXF088

409Chapter 29 MPU / EDSU4.RegistersRemark: Read and write access to all registers is byte, halfword and word.F0C0HBAD16 [R/W]XXXXXXXX XXXXXXXX XXXX

410Chapter 29 MPU / EDSU4.Registers4.2 Explanations of Registers● EDSU Control Register (BCTRL)Default Permission RegisterThe default permission reg

411Chapter 29 MPU / EDSU4.RegistersBIT[11]: UW - User default Write permission registerBIT[10]: UX - User default eXecute permission registerCPU and

412Chapter 29 MPU / EDSU4.RegistersIf EEMM is set to ’1’ then the emulation mode is entered during Step Trace Mode and EDSU exceptions InstructionBre

413Chapter 29 MPU / EDSU4.RegistersBIT[3]: EINT1 - Enable extended INTerrupt 1If EINT1 is set to ’1’ then a Tool NMI will be generated on an extended

27Chapter 3 MB91460 Series Basic Information2.I/O Map000080HBGR100 [R/W]00000000BGR000 [R/W]00000000BGR101 [R/W]00000000BGR001 [R/W]00000000BaudrateG

414Chapter 29 MPU / EDSU4.Registers● EDSU Status Register (BSTAT)BIT[15:11]: IDX[4:0] - Channel Index Indication of MPUPV TriggerIn the case of trigg

415Chapter 29 MPU / EDSU4.RegistersBIT[9:8]: CSZ[1:0] - Capture Operand SizeBIT[7:6]: CRW[1:0] - Capture Operand Access TypeBIT[5]: PV - Protection V

416Chapter 29 MPU / EDSU4.RegistersBIT[3]: INT1 - INTerrupt on extended source 1INT1 reflects the status of the extended interrupt source channel 1.

417Chapter 29 MPU / EDSU4.Registers● EDSU Instruction Address Capture Register (BIAC)This register captures the address of the instruction (IA), whic

418Chapter 29 MPU / EDSU4.Registers• operand address break,• data value break,• combined operand address and data value break and• memory protection

419Chapter 29 MPU / EDSU4.Registers● EDSU Channel Configuration Register (BCR0...BCR7)For each group of four channels one channel configuration regis

420Chapter 29 MPU / EDSU4.RegistersGroup of Channels, Permission Definition RegisterThe permission definition registers are valid only for the group

421Chapter 29 MPU / EDSU4.Registers• CTC=2: IA range 0 defines execute permissions and OA range 1 defines read/write permissions.Data value (DT) detect

422Chapter 29 MPU / EDSU4.RegistersBIT[19]: URX1 - User Read/eXecute permission register for range 1Setting valid for CTC == 0 (Instruction address r

423Chapter 29 MPU / EDSU4.RegistersSome restrictions apply with the setting of the MPE bit.MPE=0 (break unit):• permission registers are don’t care (

28Chapter 3 MB91460 Series Basic Information2.I/O Map0000D0HIBCR0 [R/W]00000000IBSR0 [R]00000000ITBAH0 [R/W]- - - - - - 00ITBAL0 [R/W]00000000I2C 000

424Chapter 29 MPU / EDSU4.RegistersThe COMB bit set to ’1’ causes the IA comparator CMP0 to use the same BADx point definitions as the OA com-parator

425Chapter 29 MPU / EDSU4.RegistersThe operand break size register OBS configures the datasize and the operand break type register OBT configuresthe

426Chapter 29 MPU / EDSU4.RegistersThe input value and the point value is masked if the mask function is enabled by EM0. On a compare match a breakex

427Chapter 29 MPU / EDSU4.RegistersThe selection of the appropriate BADx register (point 0 or 2) for the mask value depends on EP0 and ER0. If at lea

428Chapter 29 MPU / EDSU4.RegistersThis register sets the 32 bit comparison value for break point 1 of CMP0. In range mode (set with ER0) the registe

429Chapter 29 MPU / EDSU5.Quick Reference5. Quick Reference0xF008BIAC0xF00CBOACBAD00xF080BAD10xF084BAD30xF08CBAD280xF0F0BAD290xF0F4BAD300xF0F8INT1 I

430Chapter 29 MPU / EDSU5.Quick ReferenceCTCCTCOBS−MatchIA/OACMP1BD3BD2CMP0IA/OA/DT BD1BD0IAOAIAOADTComparator GROUP 0Point 3Point 2Mask 1ValuePoint

431Chapter 30 I/O Ports1.I/O Ports FunctionsChapter 30 I/O Ports1. I/O Ports FunctionsFor enabling the resource functions, please refer to section .

432Chapter 30 I/O Ports1.I/O Ports FunctionsP00_3P00_3TP04_0General purpose I/O. This function is enabled in the single-chip mode or bysetting the co

433Chapter 30 I/O Ports1.I/O Ports FunctionsP01_0P01_0TP04_0General purpose I/O. This function is enabled in the single-chip mode or bysetting the co

29Chapter 3 MB91460 Series Basic Information2.I/O Map000120HPTMR02 [R]11111111 11111111PCSR02 [W]XXXXXXXX XXXXXXXXPPG 2000124HPDUT02 [W]XXXX

434Chapter 30 I/O Ports1.I/O Ports FunctionsP03_5P03_5TP04_0General purpose I/O. This function is enabled in the single-chip mode or bysetting the co

435Chapter 30 I/O Ports1.I/O Ports FunctionsP04_2P04_2TP04_0General purpose I/O. This function is enabled in the single-chip mode or bysetting the co

436Chapter 30 I/O Ports1.I/O Ports FunctionsP06_7P06_7TP04_0General purpose I/O. This function is enabled in the single-chip mode or bysetting the co

437Chapter 30 I/O Ports1.I/O Ports FunctionsP07_4P07_4TP04_0General purpose I/O. This function is enabled in the single-chip mode or bysetting the co

438Chapter 30 I/O Ports1.I/O Ports FunctionsP08_1P08_1TP04_0General purpose I/O. This function is enabled in the single-chip mode or bysetting the co

439Chapter 30 I/O Ports1.I/O Ports FunctionsP10_6P10_6TP04_0General purpose I/O. This function is enabled in the single-chip mode or bysetting the co

440Chapter 30 I/O Ports1.I/O Ports FunctionsP11_0P11_0TP04_0General purpose I/O.IORDX Output pin for DMA I/O to memory fly-by transfer.Port 12P12_7P12

441Chapter 30 I/O Ports1.I/O Ports FunctionsP14_7P14_7TP00_0General purpose I/O.ICU7 Data sample input pin for input capture ICU 7.TIN7 Event input p

442Chapter 30 I/O Ports1.I/O Ports FunctionsP15_5P15_5TP00_0General purpose I/O.OCU5 Waveform output pin for output compare OCU 5.TOT5 Output pin for

443Chapter 30 I/O Ports1.I/O Ports FunctionsP17_7P17_7TP00_0General purpose I/O.PPG7 Waveform output pin for programmable pulse generator PPG 7.P17_6

30Chapter 3 MB91460 Series Basic Information2.I/O Map000170HP0TMCSRH[R/W]- 0 - 000 - 0P0TMCSRL[R/W]- - - 00000P1TMCSRH[R/W]- 0 - 000 - 0P1TMCSRL[R/W]

444Chapter 30 I/O Ports1.I/O Ports FunctionsP19_7 P19_7 TP00_0 General purpose I/O.P19_6P19_6TP00_0General purpose I/O.SCK5 Clock I/O pin for LIN-USA

445Chapter 30 I/O Ports1.I/O Ports FunctionsPort 21P21_7 P21_7 TP00_0 General purpose I/O.P21_6P21_6TP00_0General purpose I/O.SCK1 Clock I/O pin for

446Chapter 30 I/O Ports1.I/O Ports FunctionsP23_7P23_7TP00_0General purpose I/O.TX3 Transmission output pin for CAN 3.P23_6P23_6TP00_0General purpose

447Chapter 30 I/O Ports1.I/O Ports FunctionsPort 25P25_7P25_7TP05_0General purpose I/O.SMC2M5 PWM output 2M (-) stepper motor controller 5.P25_6P25_6

448Chapter 30 I/O Ports1.I/O Ports FunctionsP26_0P26_0TP05_0General purpose I/O.SMC1P2 PWM output 1P (+) stepper motor controller 2.AN24 Analog input

449Chapter 30 I/O Ports1.I/O Ports FunctionsP28_3P28_3TP03_0General purpose I/O.AN11 Analog input pin 11 for the A/D converter 1.P28_2P28_2TP03_0Gene

450Chapter 30 I/O Ports1.I/O Ports FunctionsP30_0P30_0TP06_0General purpose I/O.COM0 Common driver output pin 0 LCD controller.Port 31P31_7P31_7TP06_

451Chapter 30 I/O Ports1.I/O Ports FunctionsP32_0P32_0TP06_0General purpose I/O.SEG24 Segment driver output pin 24 LCD controller.SIN14 Serial data i

452Chapter 30 I/O Ports1.I/O Ports FunctionsP34_2P34_2TP06_0General purpose I/O.SEG10 Segment driver output pin 10 LCD controller.SCK10 Clock I/O pin

453Chapter 30 I/O Ports2.I/O Circuit Types2. I/O Circuit Types2.1 I/O Cell List MB91V460Note: This table shows the I/O cells used for MB91V460. Ple

31Chapter 3 MB91460 Series Basic Information2.I/O Map0001B8HTMRLR1 [W]XXXXXXXX XXXXXXXXTMR1 [R]XXXXXXXX XXXXXXXXReload Timer1(PPG 2-3)0001BCH

454Chapter 30 I/O Ports3.Port Register Settings3. Port Register Settings3.1 General RulesFor all ports, the following rules are valid:1. All port i

455Chapter 30 I/O Ports3.Port Register Settings14.Resource output lines are enabled by setting the corresponding PFR and/or EPFR bit in the port. Det

456Chapter 30 I/O Ports3.Port Register Settings3.2 I/O Port Block DiagramPort BusPDRDDRPeripheral inputsPDRD readPinPDR: Port Data Register Address

457Chapter 30 I/O Ports3.Port Register Settings3.3 Port Input EnableThis section describes the Port Input Enable function. PORTEN: Port Input Enabl

458Chapter 30 I/O Ports3.Port Register Settings3.4 Port Function Register SetupThis section describes the Port Function Registers of each port. P00

459Chapter 30 I/O Ports3.Port Register Settings P01: The functions of Port 01 are controlled by PFR01If the external bus interface is enabled (by mo

460Chapter 30 I/O Ports3.Port Register Settings P02: The functions of Port 02 are controlled by PFR02If the external bus interface is enabled (by mo

461Chapter 30 I/O Ports3.Port Register Settings P03: The functions of Port 03 are controlled by PFR03If the external bus interface is enabled (by mo

462Chapter 30 I/O Ports3.Port Register Settings P04: The functions of Port 04 are controlled by PFR04If the external bus interface is enabled (by mo

463Chapter 30 I/O Ports3.Port Register Settings P05: The functions of Port 05 are controlled by PFR05If the external bus interface is enabled (by mo

32Chapter 3 MB91460 Series Basic Information2.I/O Map0001F8HTCDT2 [R/W]XXXXXXXX XXXXXXXXres.TCCS2 [R/W]00000000Free RunningTimer 2(OCU 0-1)0001FC

464Chapter 30 I/O Ports3.Port Register Settings P06: The functions of Port 06 are controlled by PFR06If the external bus interface is enabled (by mo

465Chapter 30 I/O Ports3.Port Register Settings P07: The functions of Port 07 are controlled by PFR07If the external bus interface is enabled (by mo

466Chapter 30 I/O Ports3.Port Register Settings P08: The functions of Port 08 are controlled by PFR08If the external bus interface is enabled (by mo

467Chapter 30 I/O Ports3.Port Register Settings P09: The functions of Port 09 are controlled by PFR09If the external bus interface is enabled (by mo

468Chapter 30 I/O Ports3.Port Register Settings P10: The functions of Port 10 are controlled by PFR10 and EPFR10If the external bus interface is ena

469Chapter 30 I/O Ports3.Port Register Settings P11: The functions of Port 11 are controlled by PFR11P11[7:0] is input/output for DMA control signal

470Chapter 30 I/O Ports3.Port Register Settings P12: The functions of Port 12 are controlled by PFR12 and EPFR12P12[7:0] is input/output for DMA con

471Chapter 30 I/O Ports3.Port Register Settings P13: The functions of Port 13 are controlled by PFR13 and EPFR13P13[7:0] is input/output for DMA con

472Chapter 30 I/O Ports3.Port Register Settings P14: The functions of Port 14 are controlled by PFR14 and EPFR14P14[7:0] is input/output for Input C

473Chapter 30 I/O Ports3.Port Register SettingsResource function is TIN1 and TTG9/1 input, andEPFR14.1 0 - Resource function is ICU1 input1 - ICU1 is

33Chapter 3 MB91460 Series Basic Information2.I/O Map000258H-00027CHreserved000280HSCR08 [R/W,W]00000000SMR08 [R/W,W]00000000SSR08 [R/W,R]00001000RDR

474Chapter 30 I/O Ports3.Port Register Settings P15: The functions of Port 15 are controlled by PFR15 and EPFR15P15[7:0] is input/output for Output

475Chapter 30 I/O Ports3.Port Register Settings P16: The functions of Port 16 are controlled by PFR16 and EPFR16P16[7:0] is input/output for Program

476Chapter 30 I/O Ports3.Port Register Settings P17: The functions of Port 17 are controlled by PFR17P17[7:0] is input/output for Programmable Pulse

477Chapter 30 I/O Ports3.Port Register Settings P18: The functions of Port 18 are controlled by PFR18 and EPFR18P18[7:0] is input/output for LIN-UAR

478Chapter 30 I/O Ports3.Port Register Settings P19: The functions of Port 19 are controlled by PFR19 and EPFR19P19[7:0] is input/output for LIN-UAR

479Chapter 30 I/O Ports3.Port Register Settings P20: The functions of Port 20 are controlled by PFR20 and EPFR20P20[7:0] is input/output for LIN-UAR

480Chapter 30 I/O Ports3.Port Register Settings P21: The functions of Port 21 are controlled by PFR21 and EPFR21P21[7:0] is input/output for LIN-UAR

481Chapter 30 I/O Ports3.Port Register Settings P22: The functions of Port 22 are controlled by PFR22P22[7:0] is input/output for I2C serial communi

482Chapter 30 I/O Ports3.Port Register SettingsResource function is RX4 input, and INT12 inputRemark: This pin supports external interrupt wake up fr

483Chapter 30 I/O Ports3.Port Register Settings P23: The functions of Port 23 are controlled by PFR23P23[7:0] is input/output for CAN serial communi

iTOCChapter 1 Introduction... 11. How to Handle the Device ...

34Chapter 3 MB91460 Series Basic Information2.I/O Map0002B0HSCR14 [R/W,W]00000000SMR14 [R/W,W]00000000SSR14 [R/W,R]00001000RDR14/TDR14[R/W]00000000US

484Chapter 30 I/O Ports3.Port Register SettingsResource function is RX0 input, and INT8 inputRemark: This pin supports external interrupt wake up fro

485Chapter 30 I/O Ports3.Port Register Settings P24: The functions of Port 24 are controlled by PFR24P24[7:0] is input/output for I2C serial communi

486Chapter 30 I/O Ports3.Port Register SettingsRemark: This pin supports external interrupt wake up from STOP-HIZ mode. Because of thisthe internal i

487Chapter 30 I/O Ports3.Port Register Settings P25: The functions of Port 25 are controlled by PFR25P25[7:0] is input/output for Stepper Motor PWM

488Chapter 30 I/O Ports3.Port Register Settings P26: The functions of Port 26 are controlled by PFR26 and EPFR26P26[7:0] is input/output for Stepper

489Chapter 30 I/O Ports3.Port Register Settings P27: The functions of Port 27 are controlled by PFR27 and EPFR27P27[7:0] is input/output for Stepper

490Chapter 30 I/O Ports3.Port Register Settings P28: The functions of Port 28 are controlled by PFR28P28[7:0] is input/output for A/D converter anal

491Chapter 30 I/O Ports3.Port Register Settings P29: The functions of Port 29 are controlled by PFR29P29[7:0] is input/output for A/D converter anal

492Chapter 30 I/O Ports3.Port Register Settings P30: The functions of Port 30 are controlled by PFR30P30[7:0] is input/output for LCD controller ref

493Chapter 30 I/O Ports3.Port Register Settings P31: The functions of Port 31 are controlled by PFR31P31[7:0] is input/output for LCD controller seg

35Chapter 3 MB91460 Series Basic Information2.I/O Map0002F4HTCDT5 [R/W]XXXXXXXX XXXXXXXXres.TCCS5 [R/W]00000000Free RunningTimer 5(ICU 6-7)0002F8

494Chapter 30 I/O Ports3.Port Register Settings P32: The functions of Port 32 are controlled by PFR32 and EPFR32P32[7:0] is input/output for LCD con

495Chapter 30 I/O Ports3.Port Register Settings P33: The functions of Port 33 are controlled by PFR33 and EPFR33P33[7:0] is input/output for LCD con

496Chapter 30 I/O Ports3.Port Register Settings P34: The functions of Port 34 are controlled by PFR34 and EPFR34P34[7:0] is input/output for LCD con

497Chapter 30 I/O Ports3.Port Register Settings P35: The functions of Port 35 are controlled by PFR35 and EPFR35P35[7:0] is input/output for LCD con

498Chapter 30 I/O Ports3.Port Register Settings3.5 Port Input Level SelectionThe input levels of each port can be programmed bit-wise between CMOS H

499Chapter 30 I/O Ports3.Port Register SettingsPILR20 0E54h PILR20.7 PILR20.6 PILR20.5 PILR20.4 PILR20.3 PILR20.2 PILR20.1 PILR20.0 0000 0000PILR21 0

500Chapter 30 I/O Ports3.Port Register Settings3.6 Programmable Pull-Up/Pull Down ResistorsThe Ports listed in the following table have 50 kOhm Pull

501Chapter 30 I/O Ports3.Port Register SettingsPPER02 0EC2h PPER02.7 PPER02.6 PPER02.5 PPER02.4 PPER02.3 PPER02.2 PPER02.1 PPER02.0 0000 0000PPER03 0

502Chapter 30 I/O Ports3.Port Register SettingsBitPort Pull-Up/Pull-Down Control Registers0 1 (default)PPCRx.y Pull Down is selected Pull-Up is selec

503Chapter 30 I/O Ports3.Port Register SettingsNote: PPCR Register bits can only be written, if the attached PPER register bit is low (resistors disa

36Chapter 3 MB91460 Series Basic Information2.I/O Map000340HPTMR14 [R]11111111 11111111PCSR14 [W]XXXXXXXX XXXXXXXXPPG 14000344HPDUT14 [W]XXX

504Chapter 30 I/O Ports3.Port Register SettingsPODR14 0E0Eh PODR14.7 PODR14.6 PODR14.5 PODR14.4 PODR14.3 PODR14.2 PODR14.1 PODR14.0 0000 0000PODR15 0

505Chapter 30 I/O Ports3.Port Register Settings

506Chapter 30 I/O Ports3.Port Register Settings

507Chapter 31 External Bus1.Overview of the External Bus InterfaceChapter 31 External BusThe external bus interface controller controls the interface

508Chapter 31 External Bus1.Overview of the External Bus Interface• Capable of setting timing values such as the CAS latency and RAS - CAS delay (SDR

509Chapter 31 External Bus1.Overview of the External Bus Interface1.2 Block DiagramFigure 1-1 Block Diagram of the External Bus Interface32 32Inter

510Chapter 31 External Bus1.Overview of the External Bus Interface1.3 I/O PinsThe I/O pins are external bus interface pins (Some pins have other use

511Chapter 31 External Bus1.Overview of the External Bus InterfaceFigure 1-2 List of External Bus Interface Registers31 24 23

512Chapter 31 External Bus2.External Bus Interface Registers2. External Bus Interface RegistersThis section explains the registers used in the exter

513Chapter 31 External Bus2.External Bus Interface RegistersFigure 2-1 Configuration of the Area Select Registers (ASR0-7) Functions of Bits in the

37Chapter 3 MB91460 Series Basic Information2.I/O Map0003D8H-0003E0Hreserved0003E4HreservedICHCR [R/W]0 - 000000I-Cache0003E8H-0003ECHreserved0003F0H

514Chapter 31 External Bus2.External Bus Interface Registersselect area.Figure 2-2 "Configuration of Area Configuration Registers 0-7 (ACR0-7)&q

515Chapter 31 External Bus2.External Bus Interface RegistersThe following explains the function of each bit:[Bits 15-12] ASZ3-0 (Area Size Bits 3-0)T

516Chapter 31 External Bus2.External Bus Interface RegistersASZ3-0 are used to set the size of each area by modifying the number of bits for address

517Chapter 31 External Bus2.External Bus Interface RegistersIn areas for which a burst length other than the single access is set, continuous burst a

518Chapter 31 External Bus2.External Bus Interface RegistersIf an area for which write operations are disabled is accessed for a write operation from

519Chapter 31 External Bus2.External Bus Interface RegistersSet the access type as the combination of all bits.For details of the operations of each

520Chapter 31 External Bus2.External Bus Interface Registers2.3 Area Wait Register (AWR0-7)This section explains the configuration and functions of

521Chapter 31 External Bus2.External Bus Interface RegistersThe function of each bit changes according to the access type (TYP(3-0) bits) setting of

522Chapter 31 External Bus2.External Bus Interface Registers[Bits 15-12] W15-12 (First Wait Cycle)These bits set the number of auto-wait cycles to be

523Chapter 31 External Bus2.External Bus Interface Registers[Bits 7,6] W07-06 (Read -> Write Idle Cycle)The read -> write idle cycle is set to

38Chapter 3 MB91460 Series Basic Information2.I/O Map000440HICR00 [R/W]---11111ICR01 [R/W]---11111ICR02 [R/W]---11111ICR03 [R/W]---11111InterruptCont

524Chapter 31 External Bus2.External Bus Interface Registers[Bits 3] W03 (WR0-WR3, WRn Output Timing Selection)The WR0-WR3, WRn output timing setting

525Chapter 31 External Bus2.External Bus Interface Registers[Bits 2] W02 (Address -> CSn Delay)The address -> CSn delay setting is made when a

526Chapter 31 External Bus2.External Bus Interface Registers[Bits 0] W00 (RD/WRn -> CSn Hold Extension Cycle)The RD/WRn -> CSn hold extension c

527Chapter 31 External Bus2.External Bus Interface RegistersFor all the areas connected to SDRAM/FCRAM, set these bits to the same RAS - CAS delay cy

528Chapter 31 External Bus2.External Bus Interface RegistersTable 4.2 - 22 lists the settings for the write recovery cycle.For all the areas connecte

529Chapter 31 External Bus2.External Bus Interface Registers Structure of the Memory Setting Register (MCRA for SDRAM/FCRAM auto - precharge OFFmode

530Chapter 31 External Bus2.External Bus Interface RegistersTable 2-27 lists the settings for burst write.For connecting FCRAM, be sure to set the bi

531Chapter 31 External Bus2.External Bus Interface RegistersFigure 2-5 Structure of the Memory Setting Register (MCRB for FCRAM auto - precharge ON

532Chapter 31 External Bus2.External Bus Interface Registers Functions of Bits in the I/O Wait Registers for DMAC (IOWR0-3)The following explains th

533Chapter 31 External Bus2.External Bus Interface Registersis set to the high impedance state.

39Chapter 3 MB91460 Series Basic Information2.I/O Map00048CHPLLDIVM [R/W]- - - - 0000PLLDIVN [R/W]- - 000000PLLDIVG [R/W]- - - - 0000PLLMULG [W]0

534Chapter 31 External Bus2.External Bus Interface Registers[Bits 27-24, 19-16, 11-8] IW03-00,IW13-10 (I/O Access Wait)These bits set the number of a

535Chapter 31 External Bus2.External Bus Interface RegistersBefore setting this register, be sure to make all settings required for the corresponding

536Chapter 31 External Bus2.External Bus Interface Registers[Bits 23-16] CHE7-0 (Cache Enable 7-0)These bits enable and disable each chip select area

537Chapter 31 External Bus2.External Bus Interface Registers[Bit 6] PSUS (Prefetch suspend)This bit controls temporary stopping of prefetch to all ar

538Chapter 31 External Bus2.External Bus Interface Registers2.10 Refresh Control Register (RCR)This section describes the bit configuration and func

539Chapter 31 External Bus2.External Bus Interface RegistersWhen read by a Read - modify - Write instruction, the SELF, RRLD, and PON bits always ret

540Chapter 31 External Bus2.External Bus Interface Registers[Bits 22 - 20] RFC2, RFC1, RFC0 (ReFresh Count): Refresh countSet these bits to the numbe

541Chapter 31 External Bus2.External Bus Interface RegistersTable 4.2-47 lists the settings for the refresh cycle (tRC).Table 2-31 Settings for the

542Chapter 31 External Bus3.Setting Example of the Chip Select Area3. Setting Example of the Chip Select AreaIn the external bus interface, a total

543Chapter 31 External Bus4.Endian and Bus Access4. Endian and Bus AccessThere is a one-to-one correspondence between theWR0-WR3 control signal and

40Chapter 3 MB91460 Series Basic Information2.I/O Map0004D0HC340R [R/W]- - - - - - - 0res.EISSRH [R/W]00000000EISSRL [R/W]00000000340 Compati-bility

544Chapter 31 External Bus4.Endian and Bus Access● SDRAM InterfaceFigure 4-3 Data bus width of the SDRAM (FCRAM) interface and its control signals4.

545Chapter 31 External Bus4.Endian and Bus AccessFigure 4-5 Relationship between the Internal Register and External Data Bus for Halfword AccessFigu

546Chapter 31 External Bus4.Endian and Bus Access● 16-bit bus widthFigure 4-8 Relationship between Internal Register and External Bus Having 16-Bit

547Chapter 31 External Bus4.Endian and Bus Access● 32-bit bus widthFigure 4-10 External bus Access for 32-Bit Bus Width● 16-bit bus widthFigure 4-11

548Chapter 31 External Bus4.Endian and Bus Access● 8-bit bus widthFigure 4-12 External Bus Access for 8-Bit Bus Width Example of Connection with Ex

549Chapter 31 External Bus4.Endian and Bus AccessFigure 4-13 Example of Connecting the MB91460 Series to External Devices4.2 Little Endian Bus Acce

550Chapter 31 External Bus4.Endian and Bus Access● Halfword accessThe byte data on the MSB side for the big endian address 0 becomes byte data on the

551Chapter 31 External Bus4.Endian and Bus AccessFigure 4-16 Relationship between Internal Register and External Data Bus for Byte Access Data Bus

552Chapter 31 External Bus4.Endian and Bus Access● 8-bit bus widthFigure 4-19 Relationship between the Internal Register and External Data Bus in th

553Chapter 31 External Bus4.Endian and Bus Access● 16-bit bus widthFigure 4-21 Example of Connecting the MB91460 Series to External Devices (16-Bit

41Chapter 3 MB91460 Series Basic Information2.I/O Map000640HASR0 [R/W]00000000 00000000ACR0 [R/W]1111**00 00000000External BusUnit000644HASR1

554Chapter 31 External Bus4.Endian and Bus Access4.3 Comparison of Big Endian and Little Endian External AccessThis section shows a comparison of bi

555Chapter 31 External Bus4.Endian and Bus Access Word AccessBig endian mode Little endian mode32-bit buswidth16-bit buswidth8-bit buswidth(1)D00D31

556Chapter 31 External Bus4.Endian and Bus Access Halfword AccessBig endian mode Little endian mode32-bit buswidth(1)D00D31D31AABBWR0WR1BBAA--D00add

557Chapter 31 External Bus4.Endian and Bus Access16-bit buswidth8-bit buswidthBig endian mode Little endian modeAABBWR0WR1BBAAaddress: "2"

558Chapter 31 External Bus4.Endian and Bus Access Byte Access

559Chapter 31 External Bus4.Endian and Bus AccessBig endian mode Little endian mode32-bit buswidth(1)D00D31D31AAWR0AA---D00address : "0"In

560Chapter 31 External Bus4.Endian and Bus Access16-bit buswidthBig endian mode Little endian modeAAAAWR0address: "0"D00D31D31Internal

561Chapter 31 External Bus4.Endian and Bus Access8-bit buswidthBig endian mode Little endian modeAAAAWR0address: "0"D00D31D31Internal

562Chapter 31 External Bus5.Operation of the Ordinary bus interface5. Operation of the Ordinary bus interfaceThis section explains operation of the

563Chapter 31 External Bus5.Operation of the Ordinary bus interfaceFigure 5-1 Basic Timing (For Successive Accesses)• AS is asserted for one cycle i

42Chapter 3 MB91460 Series Basic Information2.I/O Map0007FCHres.MODR [W]XXXXXXXXres. res. Mode Register000800H-000BFCHreserved DSU4 / RTM000C00HTVCT

564Chapter 31 External Bus5.Operation of the Ordinary bus interfaceFigure 5-2 Timing Chart for the WRn + Byte Control Type• Operation of AS, CSn, RD

565Chapter 31 External Bus5.Operation of the Ordinary bus interface5.3 Read -> Write OperationThis section shows the operating timing for read -&

566Chapter 31 External Bus5.Operation of the Ordinary bus interfaceFigure 5-4 Timing Chart for the Write -> Write Operation• Setting of the W05/W

567Chapter 31 External Bus5.Operation of the Ordinary bus interfaceFigure 5-5 Timing Chart for the Auto-Wait CycleSetting of the W15-12 bits (first

568Chapter 31 External Bus5.Operation of the Ordinary bus interfaceFigure 5-6 Timing Chart for the External Wait CycleSetting 1 for the TYP0 bit of

569Chapter 31 External Bus5.Operation of the Ordinary bus interfaceFigure 5-7 Timing Chart for Synchronous Write Enable Output• If synchronous write

570Chapter 31 External Bus5.Operation of the Ordinary bus interface• If synchronous write enable output is used, the following restrictions apply:Do

571Chapter 31 External Bus5.Operation of the Ordinary bus interface5.9 CSn -> RD/WRn Setup and RD/WRn -> CSn Hold SettingThis section shows the

572Chapter 31 External Bus5.Operation of the Ordinary bus interface Operation Timing for DMA Fly-By Transfer (I/O -> Memory)Figure 5-10 "Tim

573Chapter 31 External Bus5.Operation of the Ordinary bus interfaceFigure 5-11 Timing Chart for DMA Fly-By Transfer (Memory -> I/O)• Setting 1 fo

43Chapter 3 MB91460 Series Basic Information2.I/O Map000D40HDDR00 [R/W]00000000DDR01 [R/W]00000000DDR02 [R/W]00000000DDR03 [R/W]00000000R-busPort Dir

574Chapter 31 External Bus6.Burst Access Operation6. Burst Access OperationIn the external bus interface, the operation that transfers successive da

575Chapter 31 External Bus6.Burst Access Operationthe minimum number of the first access cycles is the wait cycles + 2 cycles (three cycles in the ti

576Chapter 31 External Bus7.Address/data Multiplex Interface7. Address/data Multiplex InterfaceThis section explains the following three cases of op

577Chapter 31 External Bus7.Address/data Multiplex Interface• As with the normal interface, auto-wait (AWR15-12), read -> write idle cycle (AWR7-6

578Chapter 31 External Bus7.Address/data Multiplex InterfaceFigure 7-3 Timing Chart for the Address/Data Multiplex Interface (CSn -> RD/WRn Setup

579Chapter 31 External Bus8.Prefetch Operation8. Prefetch OperationThis section explains the prefetch operation. Prefetch OperationThe external bus

580Chapter 31 External Bus8.Prefetch OperationDuring burst access, successive accesses occur only within the address boundary that that is determined

581Chapter 31 External Bus8.Prefetch Operation• If a buffer read error occurs. A buffer read error is if any of the following events occurs:• When n

582Chapter 31 External Bus9.SDRAM/FCRAM Interface Operation9. SDRAM/FCRAM Interface OperationThis section describes the operations of the SDRAM/FCRA

583Chapter 31 External Bus9.SDRAM/FCRAM Interface OperationFigure 9-2 Single Read/Write Timing ChartSet the W07 and W06 bits in the area wait regist

ii6. EIT Vector Table... 1227. Multiple

44Chapter 3 MB91460 Series Basic Information2.I/O Map000DA4H-000DBCHreserved000DC0HEPFR00 [R/W]00000000EPFR01 [R/W]00000000EPFR02 [R/W]00000000EPFR03

584Chapter 31 External Bus9.SDRAM/FCRAM Interface OperationFigure 9-4 Single Read/Write Timing Chart• Setting TYP to 1001Bcauses a read/write comman

585Chapter 31 External Bus9.SDRAM/FCRAM Interface Operation Self RefreshWriting 1 to the SELF bit in the refresh control register (RCR) causes the S

586Chapter 31 External Bus9.SDRAM/FCRAM Interface Operation9.3 Connecting SDRAM/FCRAM to Many AreasThis section shows the connecting SDRAM/FCRAM to

587Chapter 31 External Bus9.SDRAM/FCRAM Interface OperationFigure 9-6 Examples of combinations of access addresses and Row/BANK/Column addresses9.5

588Chapter 31 External Bus9.SDRAM/FCRAM Interface Operation● Using 8 - bit SDRAM/FCRAM (Big endian)Total data bus width of 32 bits: Use four SDRAM/FC

589Chapter 31 External Bus9.SDRAM/FCRAM Interface OperationFigure 9-7 Using 64 - Mbit SDRAMWhen SDRAM modules are used with a total data width of 16

590Chapter 31 External Bus9.SDRAM/FCRAM Interface OperationFigure 9-8 Using 64 - Mbit SDRAMWhen using one SDRAM module with a data width of 16 bits,

591Chapter 31 External Bus9.SDRAM/FCRAM Interface OperationSDRAM No. 2 is not required when the device is used with only one SDRAM module.

592Chapter 31 External Bus10.DMA Access Operation10. DMA Access OperationThis section explains DMA access operation. DMA Access OperationThis secti

593Chapter 31 External Bus10.DMA Access OperationFigure 10-1 Timing Chart for DMA Fly-By Transfer (I/O -> Memory)• Setting 1 for the W01 bit of t

45Chapter 3 MB91460 Series Basic Information2.I/O Map000E00HPODR00 [R/W]00000000PODR01 [R/W]00000000PODR02 [R/W]00000000PODR03 [R/W]00000000R-bus Por

594Chapter 31 External Bus10.DMA Access Operation10.2 DMA Fly-By Transfer (Memory -> I/O)This section explains DMA fly-by transfer (memory ->

595Chapter 31 External Bus10.DMA Access OperationReference:For memory on the data output side, a read strobe of three bus cycles extended by the I/O

596Chapter 31 External Bus10.DMA Access OperationFigure 10-3 Timing Chart for DMA Fly - by Transfer (I/O to SDRAM/FCRAM)memoryaddressDACKnIORDDEOPnD

597Chapter 31 External Bus10.DMA Access Operation• For the I/O device on the data output side, a read strobe of three bus cycles extended by the I/O

598Chapter 31 External Bus10.DMA Access Operation● At SDRAM page hit (Shortest)Figure 10-4 Timing Chart for DMA Fly - by Transfer (SDRAM/FCRAM to I/

599Chapter 31 External Bus10.DMA Access OperationIf SDRAM access is shorter than I/O access, the SDRAM access is extended by the I/O access (base acc

600Chapter 31 External Bus10.DMA Access Operation• For the I/O device on the receiving side, a write strobe of two bus cycles extended by the I/O wai

601Chapter 31 External Bus10.DMA Access OperationSignal (CL = 2)The rise of the IOWR signal can be delayed one cycle by extending SDRAM read access o

602Chapter 31 External Bus10.DMA Access Operation10.5 2-Cycle Transfer (Internal RAM -> External I/O, RAM)This section explains 2-cycle transfer

603Chapter 31 External Bus10.DMA Access Operation 2-Cycle Transfer (External -> I/O)Figure 10-9 "Timing Chart for 2-Cycle Transfer (External

46Chapter 3 MB91460 Series Basic Information2.I/O Map000E64H-000E7CHreserved000E80HEPILR00 [R/W]00000000EPILR01 [R/W]00000000EPILR02 [R/W]00000000EPI

604Chapter 31 External Bus10.DMA Access Operation 2-Cycle Transfer (I/O -> External)Figure 10-10 "Timing Chart for 2-Cycle Transfer (I/O -&g

605Chapter 31 External Bus10.DMA Access Operation 2-Cycle Transfer (I/O -> SDRAM/FCRAM)Figure 4.10 - 11 shows an operation timing chart assuming

606Chapter 31 External Bus10.DMA Access OperationFigure 10-12 Timing Chart for Two - cycle Transfer (SDRAM/FCRAM to I/O)MCLKA31 to 0ASCSnRDCSnmemory

607Chapter 31 External Bus10.DMA Access Operation• Bus access is the same as that of the interface for non - DMA transfer.• In base mode, DACKn/DEOPn

608Chapter 31 External Bus11.Bus Arbitration11. Bus ArbitrationThis section shows timing charts for releasing the bus right and for acquiring the bu

609Chapter 31 External Bus11.Bus ArbitrationFigure 11-2 Timing Chart for Acquiring the Bus Right• Setting 1 for the BREN bit of the TRC register ena

610Chapter 31 External Bus12.Procedure for Setting a Register12. Procedure for Setting a RegisterThis section explains the procedure for setting a r

611Chapter 31 External Bus13.Notes on Using the External Bus Interface13. Notes on Using the External Bus InterfaceThis section explains some notes

612Chapter 31 External Bus13.Notes on Using the External Bus Interface

613Chapter 32 USART (LIN / FIFO)1.OverviewChapter 32 USART (LIN / FIFO)1. OverviewThis chapter explains the function and operation of the USART. The

47Chapter 3 MB91460 Series Basic Information2.I/O Map000EC0HPPER00 [R/W]00000000PPER01 [R/W]00000000PPER02 [R/W]00000000PPER03 [R/W]00000000R-bus Por

614Chapter 32 USART (LIN / FIFO)1.Overview USART operation modesThe USART operates in four different modes, which are determined by the MD0- and the

615Chapter 32 USART (LIN / FIFO)1.Overview USART InterruptsTable 1-3 Mode Bit SettingMD1 MD0 Mode Description0 0 0 Asynchronous (normal mode)0 1 1

616Chapter 32 USART (LIN / FIFO)2.USART Configuration2. USART Configuration USART consists of the following blocks:• Reload Counter• Reception Contr

617Chapter 32 USART (LIN / FIFO)2.USART ConfigurationFigure 2-1 USART Block Diagram Explanation of the different blocks• Reload CounterThe reload co

618Chapter 32 USART (LIN / FIFO)2.USART Configuration• Reception Data RegisterThis register retains reception data. Serial input data is converted and

619Chapter 32 USART (LIN / FIFO)2.USART Configuration• Specifying a data length• Selecting a frame data format in mode 1• Clearing the error flags• Sp

620Chapter 32 USART (LIN / FIFO)3.USART Pins3. USART Pins USART PinsThe USART pins also serve as general ports. Table 3-1 lists the pin functions,

621Chapter 32 USART (LIN / FIFO)4.USART Registers4. USART RegistersThe following table defines the USART04 registers:(Note) FSR (FIFO status registe

622Chapter 32 USART (LIN / FIFO)4.USART RegistersFigure 4-1 Serial Control Register 04 (SCR04)15 14 13 12 11 10 9 8Initial value0 0 0 0 0 0 0 0BR/W

623Chapter 32 USART (LIN / FIFO)4.USART Registers* see table 4-3 for R/W optionsTable 4-2 Functions of each bit of control register 04 (SCR04)Bit na

48Chapter 3 MB91460 Series Basic Information2.I/O Map000F24H-000F3CHreserved001000HDMASA0 [R/W]XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXXDMAC001004HDMADA0 [

624Chapter 32 USART (LIN / FIFO)4.USART Registers4.2 Serial Mode Register 04 (SMR04)This register selects an operation mode and baud rate clock and

625Chapter 32 USART (LIN / FIFO)4.USART Registers4.3 Serial Status Register 04 (SSR04)This register checks the transmission statuts, reception statu

626Chapter 32 USART (LIN / FIFO)4.USART RegistersFigure 4-3 Configuration of the Serial Status register 04 (SSR04)15 14 13 12 11 10 9 8Initial value0

627Chapter 32 USART (LIN / FIFO)4.USART RegistersTable 4-5 Functions of each bit of status register 04 (SSR04)Bit name Functionbit15 PE: Parity erro

628Chapter 32 USART (LIN / FIFO)4.USART Registers4.4 Reception and Transmission Data Register (RDR04 / TDR04)The reception data register (RDR04) hol

629Chapter 32 USART (LIN / FIFO)4.USART Registersenabled, a transmission interrupt is generated. Write the next part of transmission data when a tran

630Chapter 32 USART (LIN / FIFO)4.USART Registers* see table 4-7 for SOPE and SIOP interaction4.6 Extended Communication Control Register (ECCR04)Th

631Chapter 32 USART (LIN / FIFO)4.USART RegistersFigure 4-6 Configuration of the Extended Communication Control Register (ECCR04)Initial value0 0 0 0

632Chapter 32 USART (LIN / FIFO)4.USART Registers4.7 Baud Rate / Reload Counter Register 0 and 1 (BGR04 / 14)The baud rate / reload counter register

633Chapter 32 USART (LIN / FIFO)4.USART RegistersFigure 4-7 Baudrate Reload Counter Register 0 and 1 (BGR04 / 14)The Baud Rate / Reload Counter Regi

49Chapter 3 MB91460 Series Basic Information2.I/O Map008000H-00BFFCHMB91V460 Boot-ROM size is 4kB : 00B000H - 00BFFCH(instruction access is 1 waitcyc

634Chapter 32 USART (LIN / FIFO)4.USART Registers4.8 FIFO Control Register (FCR04)Figure 4-8 Configuration of FIFO control registe76543210Initial va

635Chapter 32 USART (LIN / FIFO)4.USART Registers(Note) The RX triggerlevel sets the reception FIFO level where the reception interrupt is activated.

636Chapter 32 USART (LIN / FIFO)4.USART Registers4.9 FIFO Status Register (FSR04)Figure 4-9 Configuration of FIFO status register(Note) The FSR04[4:

637Chapter 32 USART (LIN / FIFO)4.USART RegistersTable 4-10 Functions of each bit of FIFO status RegisterBit name Functionbit 0 FIFO: number ofvalid

638Chapter 32 USART (LIN / FIFO)5.USART Interrupts5. USART InterruptsThe USART uses both reception and transmission interrupts. An interrupt request

639Chapter 32 USART (LIN / FIFO)5.USART Interrupts• - Framing error, i. e. a stop bit was expected, but a "0"-bit was received: FRE• - Pari

640Chapter 32 USART (LIN / FIFO)5.USART InterruptsFigure 5-1 Bus idle interrupt generation5.1 Reception Interrupt Generation and Flag Set TimingThe

641Chapter 32 USART (LIN / FIFO)5.USART Interrupts"7p1" and "8N1" (p = "E" [even] or "O" [odd]), all in NRZ d

642Chapter 32 USART (LIN / FIFO)6.USART Baud Rates Transmission Interrupt Request Generation TimingIf the TDRE flag is set to 1 when a transmission

643Chapter 32 USART (LIN / FIFO)6.USART Baud RatesFigure 6-1 Baud rate selection circuit (reload counter)6.1 Setting the Baud RateThis section desc

50Chapter 3 MB91460 Series Basic Information2.I/O Map00C040HIF2CREQ0 [R/W]00000000 00000001IF2CMSK0 [R/W]00000000 00000000CAN 0IF 2 Register00C04

644Chapter 32 USART (LIN / FIFO)6.USART Baud Rates Suggested Division Ratios for different machine speeds and baud ratesThe following settings are s

645Chapter 32 USART (LIN / FIFO)6.USART Baud RatesFigure 6-2 Counting example of the reload counters(Note) The falling edge of the Serial Clock Sign

646Chapter 32 USART (LIN / FIFO)6.USART Baud RatesFigure 6-3 Reload Counter Restart exampleIn this example the number of MCU clock cycles (cyc) afte

647Chapter 32 USART (LIN / FIFO)7.USART Operation7. USART OperationUSART operates in operation mode 0 for normal bidirectional serial communication,

648Chapter 32 USART (LIN / FIFO)7.USART OperationTXE) and reception (SCR04: RXE). If each of the operations is disabled, stop it as follows:• If rece

649Chapter 32 USART (LIN / FIFO)7.USART OperationIf transmission interrupt is enabled (TIE = 1), the interrupt is generated by the TDRE flag. Note, t

650Chapter 32 USART (LIN / FIFO)7.USART Operation Transfer data formatIn the synchronous mode, 8-bit data is transferred with no start or stop bits

651Chapter 32 USART (LIN / FIFO)7.USART OperationSPI). This will make sure, that the transmission data is valid and stable at any falling clock edge.

652Chapter 32 USART (LIN / FIFO)7.USART Operation• BDS: "0" for LSB first,"1" for MSB first• RIE: "1" if interrupts are

653Chapter 32 USART (LIN / FIFO)7.USART OperationLIN break Interrupt is enabled (LBIE = 1) USART will generate a reception interrupt, if a synchroniz

51Chapter 3 MB91460 Series Basic Information2.I/O Map00C080HTREQR20 [R]00000000 00000000TREQR10 [R]00000000 00000000CAN 0Status Flags00C084HTREQR

654Chapter 32 USART (LIN / FIFO)7.USART OperationFigure 7-7 LIN bus timing and USART signals7.4 Direct Access to Serial PinsUSART allows the user to

655Chapter 32 USART (LIN / FIFO)7.USART Operation7.5 Bidirectional Communication Function (Normal Mode)In operation mode 0 or 2, normal serial bidir

656Chapter 32 USART (LIN / FIFO)7.USART Operation Master-slave Communication FunctionThe settings shown in figure 7-10 are required to operate USART

657Chapter 32 USART (LIN / FIFO)7.USART OperationTable 7-3 Selection of the master-slave communication function Communication ProcedureWhen the mas

658Chapter 32 USART (LIN / FIFO)7.USART OperationFigure 7-12 Master-slave communication flowchartStartSet operation mode 1Set SIN pin as theserial da

659Chapter 32 USART (LIN / FIFO)7.USART Operation7.7 LIN Communication FunctionUSART communication with LIN devices is available for both LIN master

660Chapter 32 USART (LIN / FIFO)7.USART Operation USART as master deviceFigure 7-15 USART LIN master flow chart STARTTIE = 0, RIE = 0Send Message?Y

661Chapter 32 USART (LIN / FIFO)7.USART Operation USART as slave deviceFigure 7-16 USART LIN slave flow chart (part1) STARTInitialization:Set Opera

662Chapter 32 USART (LIN / FIFO)7.USART OperationFigure 7-17 USART LIN slave flow chart (part 2)SC Wake upfrom CPU?YNRIE = 1 0x00, 0x80,or 0xC0NY

663Chapter 32 USART (LIN / FIFO)8.Notes on using USART8. Notes on using USARTNotes on using USART are given below. Enabling OperationsIn USART, the

52Chapter 3 MB91460 Series Basic Information2.I/O Map00C100HCTRLR1 [R/W]00000000 00000001STATR1 [R/W]00000000 00000000CAN 1ControlRegister00C104H

664Chapter 32 USART (LIN / FIFO)8.Notes on using USART Baud Rate Detection Using the Input Capture UnitsThe USARTs provide the signal LSYN that can

665Chapter 33 I2C Controller1.OverviewChapter 33 I2C Controller1. OverviewThe I2C interface is a serial I/O port supporting the Inter IC bus, operat

666Chapter 33 I2C Controller1.Overview Block DiagramR-busI2C enableBus busyRepeated startSend/receiveBus ErrorStartMasterACK enableGC-ACK enableGene

667Chapter 33 I2C Controller2.I2C Interface Registers2. I2C Interface RegistersThis section describes the function of the I2C interface registers in

668Chapter 33 I2C Controller2.I2C Interface Registers Seven bit slave address MasK register (ISMK0) Seven Bit slave Address register (ISBA0) Data

669Chapter 33 I2C Controller2.I2C Interface Registers2.1 Bus Control Register (IBCR0)The bus control register (IBCR0) has the following functions:•

670Chapter 33 I2C Controller2.I2C Interface Registers[bit 14] BEIE (Bus Error Interrupt Enable)This bit enables the bus error interrupt. It can only

671Chapter 33 I2C Controller2.I2C Interface RegistersThis bit is not valid when receiving address bytes in slave mode - if the interface detects its

672Chapter 33 I2C Controller2.I2C Interface RegistersWhile this bit is ‘1’ the SCL line will hold an ‘L’ level signal. Writing ‘0’ to this bit clears

673Chapter 33 I2C Controller2.I2C Interface Registers2.2 Bus Status Register (IBSR0)The bus status register (IBSR0) has the following functions:• Bu

53Chapter 3 MB91460 Series Basic Information2.I/O Map00C140HIF2CREQ1 [R/W]00000000 00000001IF2CMSK1 [R/W]00000000 00000000CAN 1IF 2 Register00C14

674Chapter 33 I2C Controller2.I2C Interface Registers• a repeated start condition is generated by another master in the first bit of a data byte• the

675Chapter 33 I2C Controller2.I2C Interface RegistersThis bit is cleared by a (repeated-) start or stop condition.[bit 0] ADT (Address Data Transfer)

676Chapter 33 I2C Controller2.I2C Interface Registers2.3 Ten Bit Slave Address Register (ITBA0)This register (ITBAH0 / ITBAL0) designates the ten bi

677Chapter 33 I2C Controller2.I2C Interface Registers2.4 Ten Bit Address Mask Register (ITMK0)This register contains the ten bit slave address mask

678Chapter 33 I2C Controller2.I2C Interface RegistersIBSR0 register is ‘1’.Note: If the address mask is changed after the interface had been enabled,

679Chapter 33 I2C Controller2.I2C Interface Registers2.5 Seven Bit Slave Address Register (ISBA0)This register designates the seven bit slave addre

680Chapter 33 I2C Controller2.I2C Interface Registers2.6 Seven Bit Slave Address Mask Register (ISMK0)This register contains the seven bit slave add

681Chapter 33 I2C Controller2.I2C Interface Registers2.7 Data Register (IDAR0)[bit 15] - [bit 8] Not used.These bits always read ‘0’.[bit 7] - [bit

682Chapter 33 I2C Controller2.I2C Interface Registers2.8 Clock Control Register (ICCR0)The clock control register (ICCR0) has the following function

683Chapter 33 I2C Controller2.I2C Interface Registers(Note) Because of the noise filter (depending on relationship between external signal and intern

iii8. Explanations of Registers... 169Chapter 12 Instr

54Chapter 3 MB91460 Series Basic Information2.I/O Map00C180HTREQR21 [R]00000000 00000000TREQR11 [R]00000000 00000000CAN 1Status Flags00C184HTREQR

684Chapter 33 I2C Controller2.I2C Interface Registers SCL WaveformsFigure 2-1 SCL WaveformsFigure 2-1 shows the SCL waveform for sending of address

685Chapter 33 I2C Controller3.I2C Interface Operation3. I2C Interface OperationThe I2C bus executes communication using two bi-directional bus lines

686Chapter 33 I2C Controller3.I2C Interface Operation Slave Address MaskingOnly the bits set to ‘1’ in the mask registers (ITMK0 / ISMK0) are used f

687Chapter 33 I2C Controller4.Programming Flow Charts4. Programming Flow Charts Example Of Slave Addressing And Sending Data

688Chapter 33 I2C Controller4.Programming Flow Charts Example Of Receiving DataStart INT=1?Last bytetransferred?NY BER=1?YNYBus errorNAddress slave

689Chapter 33 I2C Controller4.Programming Flow Charts Example Of An Interrupt HandlerStartINT=1?AAS=1?NBER=1?YNBus errorreenable IFYYAL=1?NArbitrati

690Chapter 33 I2C Controller4.Programming Flow Charts

691Chapter 34 CAN Controller1.OverviewChapter 34 CAN Controller1. OverviewThe CAN performs communication according to the CAN protocol version 2.0 p

692Chapter 34 CAN Controller2.Register Description2. Register DescriptionThis section lists the CAN registers and describes the function of each reg

693Chapter 34 CAN Controller2.Register DescriptionBase-addr +0x10IF1 Command Request IF1 Command Maskbit[15:8] bit[7:0] bit[15:8] bit[7:0]Busy Mess.

55Chapter 3 MB91460 Series Basic Information2.I/O Map00C200HCTRLR2 [R/W]00000000 00000001STATR2 [R/W]00000000 00000000CAN 2ControlRegister00C204H

694Chapter 34 CAN Controller2.Register DescriptionBase-addr +0x40IF2 Command Request IF2 Command Maskbit[15:8] bit[7:0] bit[15:8] bit[7:0]Busy Mess.

695Chapter 34 CAN Controller2.Register DescriptionFigure 2-1 CAN Register SummaryFigure 2-2 CAN Prescaler Register Summary2.2 Hardware Reset Descr

696Chapter 34 CAN Controller2.Register DescriptionAdditionally the busoff state is reset and the output CAN_TX is set to recessive(HIGH). The value 0

697Chapter 34 CAN Controller2.Register Description Function of the CAN Control Register (CTRLR)(Note) The busoff recovery sequence (see CAN Specific

698Chapter 34 CAN Controller2.Register Descriptionrecovery sequence, the Error Management Counters will be reset.(Note) During the waiting time after

699Chapter 34 CAN Controller2.Register Description Function of the Status Register (STATR)[bit15 - bit8] Reserved Bits[bit7] BOff Busoff Status0 The

700Chapter 34 CAN Controller2.Register DescriptionThe LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This

701Chapter 34 CAN Controller2.Register Description Function of the Error Counter (ERRCNT) Bit Timing Register (BTR)[bit15] RP Receive Error Passive

702Chapter 34 CAN Controller2.Register Description Function of the Bit Timing Register (BTR)(Note) With a module clock CAN_CLK of 8 MHz, the reset v

703Chapter 34 CAN Controller2.Register Description Function of the Test Register (TESTR)Write access to the Test Register is enabled by setting bit

56Chapter 3 MB91460 Series Basic Information2.I/O Map00C240HIF2CREQ2 [R/W]00000000 00000001IF2CMSK2 [R/W]00000000 00000000CAN 2IF 2 Register00C24

704Chapter 34 CAN Controller2.Register Description BRP Extension Register (BRPER) Function of the BRP Extension Register (BRPER)2.4 Message Interf

705Chapter 34 CAN Controller2.Register DescriptionFigure 2-3 IF1 and IF2 Message Interface Register Sets IFx Command Request Registers (IFxCREQ)A m

706Chapter 34 CAN Controller2.Register Description Function of the IFx Command Request Registers (IFxCREQ)(Note) Note: The Busy Flag can only be use

707Chapter 34 CAN Controller2.Register Description Function of the IFx Command Mask Register (IFxCMSK)The other bits of IFx Command Mask Register ha

708Chapter 34 CAN Controller2.Register Description(Note) If a transmission is requested by programming bit TxRqst/NewDat in the IFx Command MaskRegis

709Chapter 34 CAN Controller2.Register Description IFx Arbitration Registers (IFxARB)The bits of the Message Buffer registers mirror the Message Obj

710Chapter 34 CAN Controller2.Register Description IFx Message Control Register (IFxMCTR) IFx Data A and Data B Registers (IFxDTA, IFxDTB)The data

711Chapter 34 CAN Controller2.Register Description2.5 Message Object in the Message MemoryThere are 32 Message Objects (up to 128 depending on the im

712Chapter 34 CAN Controller2.Register Description(Note) When 11-bit (“standard”) Identifiers are used for a Message Object, the identifiers of recei

713Chapter 34 CAN Controller2.Register Description(Note) The Data Length Code of a Message Object must be defined the same as in all the correspondin

57Chapter 3 MB91460 Series Basic Information2.I/O Map00C280HTREQR22 [R]00000000 00000000TREQR12 [R]00000000 00000000CAN 2Status Flags00C284HTREQR

714Chapter 34 CAN Controller2.Register Description(Note) Byte Data 0 is the first data byte shifted into the shift register of the CAN Core during a

715Chapter 34 CAN Controller2.Register DescriptionIf several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt w

716Chapter 34 CAN Controller2.Register DescriptionIf more than 32 message buffers are implemented, the following table gives an overview about the ad

717Chapter 34 CAN Controller2.Register DescriptionThese registers hold the NewDat bits of the 32 Message Objects. By reading out the NewDat bits, the

718Chapter 34 CAN Controller2.Register DescriptionThese registers hold the IntPnd bits of the 32 Message Objects. By reading out the IntPnd bits, the

719Chapter 34 CAN Controller2.Register DescriptionThese registers hold the MsgVal bits of the 32 Message Objects. By reading out the MsgVal bits, the

720Chapter 34 CAN Controller3.Functional Description3. Functional DescriptionThis chapter provides an overview of the CAN module’s operating modes a

721Chapter 34 CAN Controller3.Functional DescriptionAutomatic Retransmission mode is enabled by setting the bit DAR in the CAN Control Register to on

722Chapter 34 CAN Controller3.Functional DescriptionFigure 3-2 CAN Core in Loop Back ModeThis mode is provided for self-test functions. To be indepe

723Chapter 34 CAN Controller3.Functional DescriptionThe IF1 Registers are used as Transmit Buffer. The transmission of the contents of the IF1 Regist

58Chapter 3 MB91460 Series Basic Information2.I/O Map00C300HCTRLR3 [R/W]00000000 00000001STATR3 [R/W]00000000 00000000CAN 3ControlRegister00C304H

724Chapter 34 CAN Controller4.CAN Application4. CAN ApplicationThis section describes how to use the CAN module in the application4.1 Management of

725Chapter 34 CAN Controller4.CAN ApplicationFigure 4-1 Data Transfer between IFx Registers and Message RAMAfter the partial write of a Message Obje

726Chapter 34 CAN Controller4.CAN Application4.5 Acceptance Filtering of Received MessagesWhen the arbitration and control field (Identifier + IDE +

727Chapter 34 CAN Controller4.CAN ApplicationFigure 4-2 Initialisation of a Transmit ObjectThe Arbitration Registers (ID28-0 and Xtd bit) are given

728Chapter 34 CAN Controller4.CAN ApplicationID18, ID17 - ID0 can then be disregarded. When a Data Frame with an 11-bit Identifier is received, ID17

729Chapter 34 CAN Controller4.CAN Application4.15 Reading from a FIFO BufferWhen the CPU transfers the contents of Message Object to the IFx Message

730Chapter 34 CAN Controller4.CAN ApplicationThe Status Interrupt has the highest priority. Among the message interrupts, the Message Object’ s inter

731Chapter 34 CAN Controller4.CAN ApplicationFigure 4-5 Bit TimingTable 4-1 Parameters of the CAN Bit Time(Note) This table describes the minimum

732Chapter 34 CAN Controller4.CAN Application

733Chapter 35 Free-Run Timer1.OverviewChapter 35 Free-Run Timer1. OverviewThe free-run timer consists of a 16-bit timer (up counter) and control cir

59Chapter 3 MB91460 Series Basic Information2.I/O Map00C340HIF2CREQ3 [R/W]00000000 00000001IF2CMSK3 [R/W]00000000 00000000CAN 3IF 2 Register00C34

734Chapter 35 Free-Run Timer3.Configuration Diagram3. Configuration DiagramFigure 3-1 Configuration DiagramFigure 3-2 Register ListNote: See “Chapte

735Chapter 35 Free-Run Timer4.Registers4. Registers4.1 TCCS: Timer Control RegisterA register for controlling the operation of the free-run timer.•

736Chapter 35 Free-Run Timer4.Registers• bit4: Stop counting• When the count stop bit is set to “1”, the free-run timer stops.• When the output compa

737Chapter 35 Free-Run Timer4.Registers• bit3: Clear mode• Set the clear mode of the free-run timer.• If the clear mode bit is set to “1”, when the c

738Chapter 35 Free-Run Timer4.Registers4.2 TCDT: Timer Data RegisterThis register can read 16-bit free-run timer count values.• TCDT0 (free-run time

739Chapter 35 Free-Run Timer5.Operation5. Operation5.1 Count Operation of the Free-run Timer(1) Reset(2) Clearing of the free-run timer by reset. (

740Chapter 35 Free-Run Timer5.Operation5.2 Various Clear Operations of the Free-run TimerClear operations of the free-run timer (4 types)(1) Reset(2

741Chapter 35 Free-Run Timer6.Setting6. Setting*: For the setting procedure, refer to the section indicated by the number.*: For the setting procedu

742Chapter 35 Free-Run Timer7.Q & A7. Q & A7.1 What are the types of the internal clock, and how do I select?There are 4 types of internal

743Chapter 35 Free-Run Timer7.Q & A7.4 How do I clear the free-run timer?You can clear the free-run timer by performing the following operations

60Chapter 3 MB91460 Series Basic Information2.I/O Map00C380HTREQR23 [R]00000000 00000000TREQR13 [R]00000000 00000000CAN 3Status Flags00C384HTREQR

744Chapter 35 Free-Run Timer7.Q & AUse interrupt request enable bit (TCCS.IVFE) to enable interrupts.Use interrupt request bit (TCCS.IVF) to clea

745Chapter 35 Free-Run Timer8.Caution8. Caution• Clearing the free-run timer• When you reset (the INIT pin input, the watchdog reset, the software r

746Chapter 35 Free-Run Timer8.Caution

747Chapter 36 Input Capture1.OverviewChapter 36 Input Capture1. OverviewInput Capture records the free-run timer count value using timing detected f

748Chapter 36 Input Capture3.Configuration3. ConfigurationFigure 3-1 Configuration DiagramFigure 3-2 Register ListNote: For information about ICR re

749Chapter 36 Input Capture4.Register4. Register4.1 IPCP: Input Capture Data RegisterA register that, using changes in an external signal as a trig

750Chapter 36 Input Capture4.Register4.2 ICS: Input Capture Control RegisterA register for controlling input capture• ICS01 (Input capture 0-1): Ad

751Chapter 36 Input Capture4.Register• bit3-bit2: Input capture 1 active edge selection• Select the active capture edge for the input capture signal

752Chapter 36 Input Capture5.Operation5. OperationThe input capture operation is described below.5.1 Capture Timing, Interrupt Timing(1) Rising edg

753Chapter 36 Input Capture5.Operation5.2 Input Capture Edge Specification and Operation• When specifying rising edge(1) Detection of rising edge of

61Chapter 3 MB91460 Series Basic Information2.I/O Map00C400HCTRLR4 [R/W]00000000 00000001STATR4 [R/W]00000000 00000000CAN 4ControlRegister00C404H

754Chapter 36 Input Capture6.Settings6. Settings*: For the setting procedure, refer to the section indicated by the number.*: For the setting proced

755Chapter 36 Input Capture7.Q&A7. Q&A7.1 What are the varieties of active edge polarity for external input, and how do I selectthem?The ac

756Chapter 36 Input Capture7.Q&AInterrupt request flags (ICS01.ICP0), (ICS01.ICP1), (ICS23.ICP0), (ICS23.ICP1), (ICS45.ICP0), (ICS45.ICP1),(ICS67

757Chapter 36 Input Capture7.Q&A7.6 How do I measure the pulse width of the input signal?• "H" Width measurement:Specify both edges fo

758Chapter 36 Input Capture8.Caution8. Caution• Input capture registerThe value of the input capture register during reset is indeterminate.Read out

759Chapter 37 Output Compare1.OverviewChapter 37 Output Compare1. OverviewOutput compare is a feature that compares the value set to the compare reg

760Chapter 37 Output Compare3.Configuration Diagram3. Configuration DiagramFigure 3-1 Configuration DiagramFigure 3-2 Register ListNote: For inform

761Chapter 37 Output Compare4.Registers4. Registers4.1 OCS: Output Control RegisterA register for controlling the operation of output compare.• OCS

762Chapter 37 Output Compare4.Registers• bit7: Interrupt request flag (output compare 1)• If free-run timer count value TCDT0 matches the output comp

763Chapter 37 Output Compare4.Registers• bit0: Enable operation requests (output compare 0)• A bit that enables a comparison operation between the fr

62Chapter 3 MB91460 Series Basic Information2.I/O Map00C440HIF2CREQ4 [R/W]00000000 00000001IF2CMSK4 [R/W]00000000 00000000CAN 4IF 2 Register00C44

764Chapter 37 Output Compare4.Registers4.2 OCCP: Compare RegisterRegister that sets the value to be compared to the 16 bit free-run timer count valu

765Chapter 37 Output Compare5.Operation5. Operation5.1 Output Compare Output (Independent Reversal) CMODE=“0”(1) Free-run timer clear/reset(2) Comp

766Chapter 37 Output Compare5.Operation5.2 Output Compare Output (Cooperative Reversal) CMODE=“1”(1) Free-run timers clear/reset(2) Compare 0 and co

767Chapter 37 Output Compare6.Settings6. Settings*: For the setting procedure, refer to the section indicated by the number.*: For the setting proce

768Chapter 37 Output Compare7.Q & A7. Q & A7.1 How do I set the compare value?Write the compare value to compare registers OCCP0 - OCCP7.7.

769Chapter 37 Output Compare7.Q & A7.4 How do I set the initial level of the compare pin output?Set it with compare pin output specification bit

770Chapter 37 Output Compare7.Q & A7.5 How do I set the output for compare pins OCU0-OCU7?Set it with port function register (PFR15[7:0]).7.6 H

771Chapter 37 Output Compare7.Q & AInterrupt request flags (OCS01. ICP[1:0]), (OCS23. ICP[1:0]), (OCS45. ICP[1:0]), (OCS67. ICP[1:0]), are notaut

772Chapter 37 Output Compare7.Q & A7.11 How do I enable interrupts?Enabling of interrupts is done with interrupt request permission bit (OCS01.

773Chapter 37 Output Compare8.Caution8. Caution• Compare stop space during compare operationAs shown below, for one count directly after the compare

63Chapter 3 MB91460 Series Basic Information2.I/O Map00C480HTREQR24 [R]00000000 00000000TREQR14 [R]00000000 00000000CAN 4Status Flags00C484HTREQR

774Chapter 37 Output Compare8.Caution

775Chapter 38 Reload Timer1.OverviewChapter 38 Reload Timer1. OverviewThe reload timer uses a 16 bit down counter to detect the input signal trigger

776Chapter 38 Reload Timer3.Configuration Reload timer 2 : PPG4, PPG5 Reload timer 3 : PPG6, PPG7 Reload timer 4 : PPG8, PPG9 Reload timer 5 : PPG10,

777Chapter 38 Reload Timer3.ConfigurationFigure 3-2 Configuration DiagramFigure 3-3 Register ListNote: For information about ICR registers and inter

778Chapter 38 Reload Timer4.Registers4. Registers4.1 TMCSR: Reload Timer Control Status RegisterThe control status register controls the operation

779Chapter 38 Reload Timer4.Registers• bit9-7: Operation mode selectionReload trigger when internal clock is selectedWhen the selected reload trigger

780Chapter 38 Reload Timer4.Registersinterrupt request is enabled (INTE=“1”) an interrupt request is generated.• bit1: Enable timer countIf timer cou

781Chapter 38 Reload Timer4.Registers• bit0: Software triggerIf the count operation is enabled (CNTE=“1”) and the software trigger bit is set to “1”,

782Chapter 38 Reload Timer5.Operation(For information on attributes, see “Meaning of Bit Attribute Symbols (Page No.10)”.)The reload value for the do

783Chapter 38 Reload Timer5.Operation5.2 Internal Clock/One-shot ModeIn one-shot mode, a one-shot pulse is output.(1) Set reload value to reload reg

iv3. Configuration ... 2504. Regist

64Chapter 3 MB91460 Series Basic Information2.I/O Map00C500HCTRLR5 [R/W]00000000 00000001STATR5 [R/W]00000000 00000000CAN 5ControlRegister00C504H

784Chapter 38 Reload Timer5.Operation5.3 External Event Clock Reload ModeExternal event reload mode counts external events and outputs a pulse with

785Chapter 38 Reload Timer5.Operation5.4 External Event Clock/One-shot ModeIn external event one-shot mode, external events are counted and a one-sh

786Chapter 38 Reload Timer5.Operation5.8 Operation when Returning from Stop ModeWhen returning due to an external interrupt, the reload timer will c

787Chapter 38 Reload Timer6.Setting6. Setting*: For the setting procedure, refer to the section indicated by the number.*: For the setting procedure

788Chapter 38 Reload Timer6.Setting*: For the setting procedure, refer to the section indicated by the number.*: For the setting procedure, refer to

789Chapter 38 Reload Timer7.Q & A7. Q & A7.1 What is the reload value setting (rewriting) procedure?The reload value is set by the 16 bit r

790Chapter 38 Reload Timer7.Q & AReload mode, Initial value “L” level outputSet to “0”Reload mode, initial value “H” level output (reversed) Set

791Chapter 38 Reload Timer7.Q & A7.6 What are the kinds of triggers, and how do I select them?• Selection is done via the trigger selection bit

792Chapter 38 Reload Timer7.Q & A7.10 How do I generate an activation trigger?• Generating a soft triggerThe setting is done via the software tr

793Chapter 38 Reload Timer7.Q & AEnabling of interrupts is done via the interrupt request permission bit (TMCSR0.INTE) ~ (TMCSR7.INTE).Clearing o

65Chapter 3 MB91460 Series Basic Information2.I/O Map00C540HIF2CREQ5 [R/W]00000000 00000001IF2CMSK5 [R/W]00000000 00000000CAN 5IF 2 Register00C54

794Chapter 38 Reload Timer8.Caution8. Caution• Count source select bit (TMCSR.CSL[2:0]) settings not in the table: “100”, “111” are disabled.If they

795Chapter 39 Programmable Pulse Generator1.OverviewChapter 39 Programmable Pulse Generator1. OverviewProgrammable Pulse Generators (PPGs) are used

796Chapter 39 Programmable Pulse Generator2.Features• Interrupt: Choose from four choices:• Software trigger• Counter borrow (cycle match)• Duty matc

797Chapter 39 Programmable Pulse Generator3.Configuration3. ConfigurationFigure 3-1 Configuration DiagramFigure 3-2 Register ListORTriggerORMDSE PCN

798Chapter 39 Programmable Pulse Generator3.ConfigurationNote: For more information about the ICR register and interrupt vector, see “Chapter 24 Inter

799Chapter 39 Programmable Pulse Generator4.Registers4. Registers4.1 PCSR: PPG Cycle Setting Register Controls the cycle of the PPG.• PCSR00 (PPG0)

800Chapter 39 Programmable Pulse Generator4.Registers4.2 PDUT: PPG Duty Setting RegisterSets the duty of the PPG output waveform.• PDUT00 (PPG0): Ad

801Chapter 39 Programmable Pulse Generator4.Registers4.3 PCN: PPG Control Status registerControls the operations and status of PPGs.• PCN00 (PPG0):

802Chapter 39 Programmable Pulse Generator4.Registers• Bit 13: Mode selection• When the Mode Selection bit is set to “0”, a PWM operation is enabled

803Chapter 39 Programmable Pulse Generator4.RegistersIf the Interrupt Request flag (IRQF) equals “1” and writing “0” to the flag take place at the sa

66Chapter 3 MB91460 Series Basic Information2.I/O Map00C580HTREQR25 [R]00000000 00000000TREQR15 [R]00000000 00000000CAN 5Status Flags00C584HTREQR

804Chapter 39 Programmable Pulse Generator4.Registers4.4 GCN1: General Control register 1Selects a trigger input to PPG0-PPG3, PPG4-PPG7, PPG8-PPG11

805Chapter 39 Programmable Pulse Generator4.Registers• PPG0 to PPG15 as selected are activated when the edge specified by the Trigger Input Edge Sele

806Chapter 39 Programmable Pulse Generator4.Registers4.5 GCN2: General Control Register 2Generates PPG0-PPG3, PPG4-PPG7, PPG8-PPG11 and PPG12-PPG15

807Chapter 39 Programmable Pulse Generator4.Registers4.6 PTMR: PPG Timer RegisterReads the counts of PPG0-PPG3, PPG4-PPG7, PPG8-PPG11 and PPG12-PPG1

808Chapter 39 Programmable Pulse Generator5.Operation5. OperationThe MB91460 series features a maximum of 16 programmable pulse generators (PPGs), w

809Chapter 39 Programmable Pulse Generator5.Operation• Equation Period = {Period value (PCSR) + 1} x Count clock Duty = {Duty value (PDUT) + 1} x Cou

810Chapter 39 Programmable Pulse Generator5.Operation5.3 Restart OperationThe restart operation is described below.• Restart available in PWM operat

811Chapter 39 Programmable Pulse Generator6.Setting6. Setting* For refer to the section indicated by the number.*For the setting procedure, refer to

812Chapter 39 Programmable Pulse Generator6.Setting*:For the setting procedure, refer to the section indicated by the number.PPG interrupt cause sele

813Chapter 39 Programmable Pulse Generator7.Q & A7. Q & A7.1 How do I set (rewrite) a cycle and a duty?Period and duty value settings• Set

67Chapter 3 MB91460 Series Basic Information2.I/O Map00F000HBCTRL [R/W]- - - - - - - - - - - - - - - - 11111100 00000000EDSU / MPU00F004HBSTA

814Chapter 39 Programmable Pulse Generator7.Q & A7.5 What count clocks are available and how are they selected?Count clock selectionThe count cl

815Chapter 39 Programmable Pulse Generator7.Q & A7.7 What activation triggers are available and how are they selected?• Trigger selection• Activ

816Chapter 39 Programmable Pulse Generator7.Q & ATriggers are selectable for PPG8, PPG9, PPG10, and PPG11 independently.Triggers are selectable f

817Chapter 39 Programmable Pulse Generator7.Q & A7.8 How do I invert the output polarity?Output polarity specificationThe polarity in the normal

818Chapter 39 Programmable Pulse Generator7.Q & A7.10 How do I generate an activation trigger?Generating a triggerMethods of generating an activ

819Chapter 39 Programmable Pulse Generator7.Q & AThe Interrupt Request flag (PCN.IRQF) does not clear itself automatically. Use software to clear

820Chapter 39 Programmable Pulse Generator7.Q & A7.13 What interrupts are available and how are they selected?Interrupt cause selectionFour kind

821Chapter 39 Programmable Pulse Generator8.Caution8. Caution• If the Interrupt Request flag (PCN.IRQF) equals “1” and the Interrupt Request flag is

822Chapter 39 Programmable Pulse Generator8.Caution

823Chapter 40 Pulse Frequency Modulator1.PFM OverviewChapter 40 Pulse Frequency ModulatorThis chapter provides an overview of the 16-bit pulse freque

68Chapter 3 MB91460 Series Basic Information2.I/O Map00F080HBAD0 [R/W]XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXXEDSU / MPU00F084HBAD1 [R/W]XXXXX

824Chapter 40 Pulse Frequency Modulator1.PFM Overview 16-bit Reload Counter 0 Register Configuration 16-bit Reload Counter 1 Register Configuration

825Chapter 40 Pulse Frequency Modulator1.PFM Overview Block Diagram of the 16-Bit Pulse Frequency ModulatorFigure 1-2 Block Diagram of the 16-bit P

826Chapter 40 Pulse Frequency Modulator2.Reload Counter Registers2. Reload Counter RegistersThis section describes the 16-bit pulse frequency modula

827Chapter 40 Pulse Frequency Modulator2.Reload Counter Registers[Bits 9] ReservedAlways set to "0".[Bits 8] MOD1Sets the Trigger level to

828Chapter 40 Pulse Frequency Modulator2.Reload Counter RegistersWriting "1" sets the counter to wait for a trigger.Writing "0" s

829Chapter 40 Pulse Frequency Modulator2.Reload Counter Registers● P0TMRLR, P1TMRLR structureFigure 2-3 Structure of the 16-bit Reload RegisterAcces

830Chapter 40 Pulse Frequency Modulator3.Reload Counter Operation3. Reload Counter OperationThis section describes the operations of the 16-bit relo

831Chapter 40 Pulse Frequency Modulator3.Reload Counter Operation● Underflow operation timingFigure 3-2 Underflow Operation Timing Counter Operation

832Chapter 40 Pulse Frequency Modulator3.Reload Counter Operation● Counter state transitionsFigure 3-3 Counter State TransitionsResetState transitio

833Chapter 40 Pulse Frequency Modulator4.PFM Operation and Setting4. PFM Operation and SettingThis section describes the following operations of the

69Chapter 3 MB91460 Series Basic Information2.I/O Map00F0C0HBAD16 [R/W]XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXXEDSU / MPU00F0C4HBAD17 [R/W]XXX

834Chapter 40 Pulse Frequency Modulator4.PFM Operation and Setting

835Chapter 41 Up/Down Counter1.OverviewChapter 41 Up/Down Counter1. OverviewTriggered by an input signal, 16-bit Up/Down Counter counts up or down w

836Chapter 41 Up/Down Counter3.Configuration3. ConfigurationFigure 3-1 Configuration DiagramUDCR0UDRC0CITEUDCS0: bit601CMS1-0 UDCC0: bit11-1000110110

837Chapter 41 Up/Down Counter3.ConfigurationFigure 3-2 Configuration DiagramUDCR1UDRC1CITEUDCS1: bit601CMS1-0 UDCC1: bit11-1000110110CES1-0 UDCC1: bit

838Chapter 41 Up/Down Counter3.ConfigurationFigure 3-3 Configuration DiagramFigure 3-4 Register ListNote: For ICR registers and interrupt vectors, re

839Chapter 41 Up/Down Counter3.ConfigurationFigure 3-5 Register ListNote: For ICR registers and interrupt vectors, refer to “Chapter 24 Interrupt Co

840Chapter 41 Up/Down Counter4.Register4. Register4.1 UDCC: Counter Control RegisterThis register is used to control behaviors of Up/Down Counter.•

841Chapter 41 Up/Down Counter4.RegisterFCLKP: Frequency of Peripheral clock (CLKP)This setting is enabled only in the timer mode, in which only count

842Chapter 41 Up/Down Counter4.Register• bit1,0: Select counter clear/gate edgeCGE1 CGE0Edge detection/level selectionWhen the counter clear function

843Chapter 41 Up/Down Counter4.Register4.2 UDCS: Count Status RegisterThis register is used to control Up/Down Counter and to indicate the status of

70Chapter 3 MB91460 Series Basic Information2.I/O Map010000H-013FFCHCache TAG way 1(010000H - 0107FCH)2 way setassociativeI-Cache4kB014000H-017FFCHCa

844Chapter 41 Up/Down Counter4.RegisterTo enable interrupt requests, the interrupt request permission bit must be set (UDIE= “1”).• bit1,0: Up/down f

845Chapter 41 Up/Down Counter4.Register4.3 UDCR: Up/Down Counter RegisterThis register is used to read the count value of Up/Down Counter.• UDCR10 (

846Chapter 41 Up/Down Counter4.Register4.4 UDRC: Up/Down Reload/Compare RegisterThis register is used to reload a value to Up/Down Counter and for c

847Chapter 41 Up/Down Counter4.Register (1) Stop counting. (2) Write a value to the reload/compare register. (3) Write “1”to the counter write bit

848Chapter 41 Up/Down Counter5.Operation5. OperationThis section describes each operation mode for Up/Down Counter.5.1 Timer Mode CMS[1:0]=“00” (1)

849Chapter 41 Up/Down Counter5.Operation5.2 Up/Down Count Mode CMS[1:0]=“01”Up/Down Counter clear control using the ZIN pin (1) Appropriate bits (Co

850Chapter 41 Up/Down Counter5.Operation5.3 Up/Down Count Mode CMS[1:0]=“01”Countgate at the ZIN pin (1) Appropriate bits (Counting enable CSTR, Rel

851Chapter 41 Up/Down Counter5.Operation5.4 Phase Difference Count Mode (Multiply by 2) CMS[1:0]=“10”Frequency multiplied by 2 in phase difference c

852Chapter 41 Up/Down Counter5.Operation5.5 Phase Difference Count Mode (Multiply by 4) CMS[1:0]=“11”Frequency multiplied by 4 in phase difference c

853Chapter 41 Up/Down Counter5.Operation5.6 Clear Timing (1) When a clear request (Compare-match, ZIN edge detection and writing “0” to the clear bi

71Chapter 3 MB91460 Series Basic Information2.I/O Map020000H-02FFFCHMB91V460 D-RAM size is 64kB : 020000H - 02FFFCH(data access is 0 waitcycles)D-RAM

854Chapter 41 Up/Down Counter5.Operation5.7 Reload TimingThe next time when Up/Down Counter counts down below “0000”, an underflow occurs (an interr

855Chapter 41 Up/Down Counter6.Setting6. Setting*: For the setting procedure, refer to the section indicated by the number.*: For the setting proced

856Chapter 41 Up/Down Counter6.Setting*: For the setting procedure, refer to the section indicated by the number.*: For the setting procedure, refer

857Chapter 41 Up/Down Counter7.Q&A7. Q&A7.1 How do I select a bit length (8 or 16) of Up/Down Counter?Use the 16 bit mode enable bit (UDCC.

858Chapter 41 Up/Down Counter7.Q&A7.7 How do I enable reloading of the reload value (RCR[1:0]) to Up/Down Counter whenUp/Down Counter is underflo

859Chapter 41 Up/Down Counter7.Q&A7.11 How do I enable/disable Up/Down Counter's count operation?Use the count activate bit (UDCS.CSTR).• H

860Chapter 41 Up/Down Counter7.Q&A7.15 How do I know that an overflow or underflow has occurred?Use the overflow detection flag (UDCS.OVFF) and th

861Chapter 41 Up/Down Counter7.Q&A7.19 How do I enable (select), disable or clear interrupts?Interrupt request enable and interrupt request flag

862Chapter 41 Up/Down Counter8.Caution8. Caution• The count direction is set to “countdown” immediately after resetting the counter. So, when the co

863Chapter 42 Sound Generator1.OverviewChapter 42 Sound Generator1. OverviewThis Chapter provides an overview of the Sound Generator, describes the

72Chapter 3 MB91460 Series Basic Information2.I/O MapNotes:*1Use a read access (byte or halfword) to this address to synchronize the CPU operation (e

864Chapter 42 Sound Generator2.Block Diagram2. Block Diagram8bit PWM pulseGeneratorPrescalerS1 S0Amplitude DataregisterCOENPWMDECCLKPTone PulseCount

865Chapter 42 Sound Generator3.Registers3. Registers 7 6 5 4 3 2 1 0TST DECSGCRL(R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0)Bit numberSound Control re

866Chapter 42 Sound Generator3.Registers3.1 Register Details Sound Control Register (SGCR)[bit 15] TST : Test bitThis bit is prepared for the devic

867Chapter 42 Sound Generator3.Registers[bit 2] INTE : Interrupt enable bitThis bit enables the interrupt signal of the Sound Generator. When this bi

868Chapter 42 Sound Generator3.Registersvalue represents the amplitude of the sound. The register value is reloaded into the PWM pulsegenerator at th

869Chapter 42 Sound Generator3.Registersreaches the reload value it sets the INT bit. They are intended to reduce the frequency ofinterrupts.The coun

870Chapter 42 Sound Generator3.Registers

871Chapter 43 Stepper Motor Controller1.OverviewChapter 43 Stepper Motor Controller1. OverviewThe stepping motor controller consists of PWM pulse ge

872Chapter 43 Stepper Motor Controller2.RegistersFigure 1-2 Stepping Motor ControllerRemark: The SMC channels 4 and 5 are not shared with ADC inputs

873Chapter 43 Stepper Motor Controller2.Registers2.1 Registers for Stepping Motor ControllerPWM2 Compare register (PWC20, PWC21, PWC22, PWC23, PWC24

73Chapter 3 MB91460 Series Basic Information3.Interrupt Vector Table3. Interrupt Vector TableThis section shows the allocation of interrupt and inte

874Chapter 43 Stepper Motor Controller2.Registers2.2 PWM Control RegisterThe PWM control register starts/stops the stepping motor controller, perfor

875Chapter 43 Stepper Motor Controller2.RegistersPWM pulse generator operates at 8 bit.[bit 1 to 0] Reserved bitsAlways set the reserved bits to &quo

876Chapter 43 Stepper Motor Controller2.Registers2.3 PWM1&2 Compare RegistersThe value of the two 8(10) bits compare register of PWM1&2 dete

877Chapter 43 Stepper Motor Controller2.RegistersFigure 2-1 Relationship between the Compare Register Setting Value and PWM Pulse WidthOne PWM cycle

878Chapter 43 Stepper Motor Controller2.Registers2.4 PWM1&2 Selection RegistersThe PWM1&2 selection registers determine whether to set the o

879Chapter 43 Stepper Motor Controller2.RegistersFigure 2-2 load timing of PWM compare register valueAutomatic clear and "1" simultaneousl

880Chapter 43 Stepper Motor Controller2.Registers[bit 13 to 11] P2 to P0: Output select bitsThese bits are used to select the output signal for SMC2

881Chapter 43 Stepper Motor Controller3.Operation3. OperationThe operation of the stepping motor controller is explained. Setting Operation of Step

882Chapter 43 Stepper Motor Controller3.OperationFigure 3-2 Examples of PWM1&2 Waveform Output Selection of motor drive signalsMotor drive sign

883Chapter 43 Stepper Motor Controller4.Caution4. CautionThe caution when using the stepping motor controller are described below. Caution when Cha

v4. Register ... 3015. Oper

74Chapter 3 MB91460 Series Basic Information3.Interrupt Vector TableExternal Interrupt 8 24 18ICR04 0x4440x39C 0x000FFF9CExternal Interrupt 9 25 19 0

884Chapter 43 Stepper Motor Controller4.Caution

885Chapter 44 A/D Converter1.Overview of A/D ConverterChapter 44 A/D ConverterThis chapter provides an overview of the A/D converter, describes the r

886Chapter 44 A/D Converter2.Block Diagram of A/D Converter2. Block Diagram of A/D ConverterFollowing figure shows block diagram of A/D converter.Bl

887Chapter 44 A/D Converter3.Registers of A/D Converter3. Registers of A/D ConverterThe A/D converter has the following registers.• • A/D enable reg

888Chapter 44 A/D Converter3.Registers of A/D Converter• ADCS0 (ADC0): Address 01A5h (Access: Half-word, Byte)(See “Meaning of Bit Attribute Symbols

889Chapter 44 A/D Converter3.Registers of A/D Converter• ADECH (ADC0): Address 01ABh (Access: Word, Half-word, Byte)(See “Meaning of Bit Attribute Sy

890Chapter 44 A/D Converter3.Registers of A/D Converter3.2 A/D Control Status Register (ADCS)A/D control status register controls and shows the stat

891Chapter 44 A/D Converter3.Registers of A/D ConverterCleared by writing "0" or by a reset. (Not cleared at the end of DMA transfer.) Howe

892Chapter 44 A/D Converter3.Registers of A/D ConverterContinuous mode: Repeated A/D conversion cycles from selected channels ANS4 to ANS0 to selecte

893Chapter 44 A/D Converter3.Registers of A/D Converter2-bit. The register values are updated at the completion of each conversion. The registers nor

75Chapter 3 MB91460 Series Basic Information3.Interrupt Vector TableUSART (LIN) 2 RX 58 3AICR21 0x4550x314 0x000FFF14 52USART (LIN) 2 TX 59 3B 0x310

894Chapter 44 A/D Converter3.Registers of A/D ConverterConversion time = CT value * CLKP cycle * 10 + (4 * CLKP)Remarks : Do not set conversion time

895Chapter 44 A/D Converter3.Registers of A/D Converter• ADECH (ADC0): Address 01ABh (Access: Word, Half-word, Byte)(See “Meaning of Bit Attribute Sy

896Chapter 44 A/D Converter4.Operation of A/D Converter4. Operation of A/D ConverterThe A/D converter operates using the successive approximation me

897Chapter 44 A/D Converter4.Operation of A/D Converter4.1 Single-shot conversion mode(1) Channel selection(2) A/D conversion activation (Trigger in

898Chapter 44 A/D Converter4.Operation of A/D Converter4.2 Scan conversion mode(1) Activation channel selection(2) A/D activation (Trigger: Software

899Chapter 44 A/D Converter5.Setting5. Setting*: For the setting procedure, refer to the section indicated by the number.*: For the setting procedur

900Chapter 44 A/D Converter5.Setting*: For the setting procedure, refer to the section indicated by the number.*: For the setting procedure, refer to

901Chapter 44 A/D Converter6.Q & A6. Q & A6.1 What conversion modes are available and how are they selected?Two modes of conversion are ava

902Chapter 44 A/D Converter6.Q & A6.3 How do I set a conversion time?Use Conversion Time Setting registers ADCT to set.[bit 15 to 10] CT5-0 (A/D

903Chapter 44 A/D Converter6.Q & A* Analogue input channels AN14 and AN15 can be also used as D/A converter outputs. In case of exclusive A/D con

76Chapter 3 MB91460 Series Basic Information3.Interrupt Vector TableInput Capture 0 92 5CICR38 0x4660x28C 0x000FFE8C 80Input Capture 1 93 5D 0x288 0x

904Chapter 44 A/D Converter6.Q & AThe converter A/D is activated on the first instance of any one of these causes selected.6.7 To activate the A

905Chapter 44 A/D Converter6.Q & A6.11 What interrupt registers are used?A/D interrupt vector, A/D interrupt level settingThe table below summar

906Chapter 44 A/D Converter7.Caution7. CautionTips on using the A/D converter are summarized as follows:• Power-on sequenceBe sure to turn on the MC

907Chapter 44 A/D Converter7.Caution Definitions of A/D Converter Terms• ResolutionAnalog change identifiable to an A/D converter.• Linearity errorD

908Chapter 44 A/D Converter7.Caution• Overall errorDifference between an actual vale and a theoretical value, containing a zero transition error/full

909Chapter 45 D/A Converter1.OverviewChapter 45 D/A Converter1. Overview The D/A converter converts digital values to analog output values on an R-2

910Chapter 45 D/A Converter3.Configuration3. ConfigurationFigure 3-1 Configuration DiagramFor a detailed description of the D/A pin circuit, see the

911Chapter 45 D/A Converter4.Registers4. Registers4.1 DADR: D/A Data RegisterThe D/A Data Register sets the output voltage of the D/A converter.• D

912Chapter 45 D/A Converter4.Registers• bit2: D/A 8-/10-bit mode control• In case MD08=’1’ the 8-bit value of DA7-DA0 (DADR[7:0]) is output.MD08 Oper

913Chapter 45 D/A Converter5.Operation5. OperationThe operations of the D/A converter are described below.(1) Digital value setting (software-progra

77Chapter 3 MB91460 Series Basic Information3.Interrupt Vector TableTable 3-1 Interrupt Vector TableNotes:*1The ICRs are located in the interrupt co

914Chapter 45 D/A Converter6.Setting6. Setting *:For the setting procedure, refer to the section indicated by the number.*:For the setting procedure

915Chapter 45 D/A Converter7.Q & A7. Q & A7.1 Where should I set digital values?Write digital values to the D/A Data Registers (DADR[7:0] f

916Chapter 45 D/A Converter8.Caution8. Caution• The table below lists the output voltages of the D/A converter (in 10-bit resolution mode).• The tabl

917Chapter 46 Alarm Comparator1.OverviewChapter 46 Alarm Comparator1. OverviewThis chapter provides an overview of the Alarm Comparator (also called

918Chapter 46 Alarm Comparator3.Alarm Comparator Control/Status Register (ACSR)3. Alarm Comparator Control/Status Register (ACSR)• ACSR0 (ch0): Addr

919Chapter 46 Alarm Comparator4.Operation ModesBit 1: IEN Interrupt enable bit.Bit 0: PD Power down bit.4. Operation ModesThe alarm comparator circ

920Chapter 46 Alarm Comparator4.Operation Modes4.4 Power Down Modes of the Alarm ComparatorThe alarm comparator circuit has the following power down

921Chapter 47 LCD Controller1.OverviewChapter 47 LCD Controller1. OverviewLCD allows display of up to 160 cells and selection of a duty cycle from 1

922Chapter 47 LCD Controller3.Configuration3. ConfigurationFigure 3-1 Configuration DiagramNote: For details on ports, refer to “Chapter 30 I/O Ports

923Chapter 47 LCD Controller3.ConfigurationFigure 3-2 Register List

78Chapter 3 MB91460 Series Basic Information4.Package4. Package BGA-660P-M02 package (BGA660-03EK): MB91V460Figure 4-1 External Dimension of BGA66

924Chapter 47 LCD Controller4.Registers4. Registers4.1 LCR0: LCDC Control Register 0This register is used to select a frame period and its clock an

925Chapter 47 LCD Controller4.Registers• bit1-0: Frame periodSelect an appropriate value in accordance with the frame frequency of your LCD panel.FP1

926Chapter 47 LCD Controller4.Registers4.2 VRAM: Data Memory for DisplayMemory area (VRAM) for setting display data• VRAM0 (SEG0, SEG1): Address 0

927Chapter 47 LCD Controller4.Registers• Correspondence between VRAM and Common/Segment Pins

928Chapter 47 LCD Controller4.Registers4.3 LCR1: LCDC Control Register 1• LCR1H: Address 0EAH (Access: Byte, Half-word, Word)(For attributes, refe

929Chapter 47 LCD Controller5.Operation5. OperationThis section describes operation.5.1 LCD Controller/Driver (LCDC) Operation(1) Set values to the

930Chapter 47 LCD Controller5.OperationCOM3 outputCOM0 outputCOM1 outputCOM2 outputV0V1V2V3V0V1V2V3V0V1V2V3V0V1V2V3SEG 2n outputV0V1V2V3SEG 2n+1 outp

931Chapter 47 LCD Controller5.Operation5.3 1/3 Duty Cycle Output WaveformIn the 1/3 duty cycle output mode, COM0, COM1 and COM2 outputs are used for

932Chapter 47 LCD Controller5.OperationCOM3 outputCOM0 outputCOM1 outputCOM2 outputV0V1V2V3V0V1V2V3V0V1V2V3V0V1V2V3SEG 2n outputV0V1V2V3SEG 2n+1 outp

933Chapter 47 LCD Controller5.Operation5.4 1/4 Duty Cycle Output WaveformIn the 1/4 duty cycle output mode, COM0, COM1, COM2, and COM3 outputs are a

79Chapter 3 MB91460 Series Basic Information5.Pin Assignment Diagram5. Pin Assignment Diagram MB91V460 (BGA660 package)Figure 5-1 Pin Assignment D

934Chapter 47 LCD Controller6.Setting6. Setting * :For the setting procedure, refer to the section indicated by the number. * :For the setting proce

935Chapter 47 LCD Controller7.Q&A7. Q&A7.1 How do I specify pins as COM or SEG output pins?Use COM and SEG output settings.Software can swi

936Chapter 47 LCD Controller7.Q&ASEG32Port function register PFR31[7:0](SEG32)SEG33 (SEG33)SEG34 (SEG34)SEG35 (SEG35)SEG36 (SEG36)SEG37 (SEG37)SE

937Chapter 47 LCD Controller7.Q&A7.2 How do I set VRM?The following tables show the relationship between pins and the bit positions of VRAM(n).

938Chapter 47 LCD Controller7.Q&A7.4 How do I set a duty cycle?Use the display mode select bit (LCR0.MS[1:0]).The display mode select bit also s

939Chapter 47 LCD Controller7.Q&A7.9 How do I select internal or external divided resistors?• When using internal divided resistors:• When using

940Chapter 47 LCD Controller8.Caution8. Caution• To access VRAM, be sure to use byte-by-byte access.• Switching the frame period generation clocks:F

941Chapter 48 Clock Monitor1.OverviewChapter 48 Clock Monitor1. OverviewThe Clock Monitor is a macro that outputs internal clock signals to a termin

942Chapter 48 Clock Monitor3.Configuration3. ConfigurationFigure 3-1 Configuration DiagramFigure 3-2 Register ListClock MonitorCMCFGCMSEL3:00000Disa

943Chapter 48 Clock Monitor4.Register4. Register4.1 Clock Monitor Configuration RegisterA register for output settings of an internal clock signal•

80Chapter 3 MB91460 Series Basic Information6.Pin Definitions6. Pin DefinitionsJEDECPin (INNER)PadI/O Function PFR=1 EPFR=1 Special TypePull Up/DwnCM

944Chapter 48 Clock Monitor4.Register• CSCFG: Address 04AEh (Access: Byte)(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the att

945Chapter 48 Clock Monitor5.Operation5. OperationThe following diagram shows the output waveforms of the Clock Monitor.(1) The MONCLK pin is in hig

946Chapter 48 Clock Monitor6.Settings6. Settings *:For each setting procedure, refer to an appropriate section.7. Q&A7.1 How do I set an outpu

947Chapter 48 Clock Monitor8.Caution8. CautionDue to the glitch free switching mechanism it is necessary to follow these rules when switching the cl

948Chapter 48 Clock Monitor8.Caution

949Chapter 49 Real-Time Clock1.OverviewChapter 49 Real-Time Clock1. OverviewReal-time Clock (RTC) continues to count elapsed time even in the STOP m

950Chapter 49 Real-Time Clock3.Configuration3. ConfigurationFigure 3-1 Configuration DiagramFigure 3-2 Register ListNote: For ICR registers and int

951Chapter 49 Real-Time Clock4.Registers4. Registers4.1 WTCR: RTC Control RegisterThis register is used to control behavior of the Real-time Clock

952Chapter 49 Real-Time Clock4.RegistersWhen the minute counter overflows, this flag is set to “1”.• bit10: 1-minute interrupt request flag• bit9: En

953Chapter 49 Real-Time Clock4.Registersrecommended that the Sub-Second register is updated while the ST bit is "0".However, if this update

81Chapter 3 MB91460 Series Basic Information6.Pin DefinitionsV37 252 208 P04_4 A28 A28 - - TP04_0 U/D CH / A / TTL Stop TTL (extbus) 4mAV36 251 205 P0

954Chapter 49 Real-Time Clock4.Registers4.2 WTBR: Sub-Second RegistersThese registers are used to hold values to be reloaded to the 21 bit down coun

955Chapter 49 Real-Time Clock4.Registers4.3 WTHR/WTMR/WTSR: Hour/Minute/Second RegistersThese registers hold time information (HH/MM/SS) for Real-ti

956Chapter 49 Real-Time Clock5.Operation5. OperationThis section describes Real-time Clock operation.(1) The start bit (ST) is set to “1” and then “

957Chapter 49 Real-Time Clock5.Operation(10) When the second counter counts up to “59”, the counter is cleared next time when the counter countsup, a

958Chapter 49 Real-Time Clock6.Setting6. Setting*: For the setting procedure, refer to the section indicated by the number.*: For the setting proced

959Chapter 49 Real-Time Clock7.Q&A7. Q&A7.1 How do I set the count period of 1 second?Stop Real-time Clock and then set the sub-second regi

960Chapter 49 Real-Time Clock7.Q&A7.8 What are interrupt-related registers?RTC interrupt vector and level settings.The following table shows the

961Chapter 49 Real-Time Clock8.Caution8. Caution• Setting the interrupt request flags (WTCR.INT0, WTCR.INT1, WTCR.INT2, WTCR.INT4 and WTCER.INT4)to

962Chapter 49 Real-Time Clock8.Cautionlower than that of the peripheral clock (CLKP). If not, correct values cannot be read from WTHR/WTMR/WTSR.• Not

963Chapter 50 Subclock Calibration Unit1.OverviewChapter 50 Subclock Calibration Unit1. OverviewThe Clock Calibration Module provides possibilities

82Chapter 3 MB91460 Series Basic Information6.Pin DefinitionsE37 190 157 P10_7 - - - - TP04_0 U/D CH / A / TTL Stop TTL (extbus) 4mAG36 189 156 P10_6

964Chapter 50 Subclock Calibration Unit2.Block Diagram2. Block DiagramFigure 2-1 Block Diagram of the calibration unitCLKPG2 = CLKP | (~STRT &

965Chapter 50 Subclock Calibration Unit3.Timing3. TimingFigure 3-1 Timing of the measurement process(4 MHz)(32 kHz)RUNSRUNCUTD CUTD-1 01 CUTD32 kHz

966Chapter 50 Subclock Calibration Unit4.Clocks4. ClocksThe module operates with 3 different clocks: The 4 MHz clock OSC4, the 32 kHz clock OSC32 (o

967Chapter 50 Subclock Calibration Unit5.Register Description5. Register DescriptionThis section lists the registers of the calibration unit and des

968Chapter 50 Subclock Calibration Unit5.Register Description 4MHz Timer Data Register (CUTR1/CUTR2)5.1 Calibration Unit Control Register (CUCR)The

969Chapter 50 Subclock Calibration Unit5.Register DescriptionBIT[0]: INTEN - Interrupt enableThis is the interrupt enable bit corresponding to the IN

970Chapter 50 Subclock Calibration Unit5.Register Description5.2 32 kHz / 100 kHz Timer Data Register (16 bit) (CUTD)The 32kHz/100kHz Timer Data Reg

971Chapter 50 Subclock Calibration Unit5.Register DescriptionTable 5-1 32kHz : Ideal measurement results depending on measurement durationThe durati

972Chapter 50 Subclock Calibration Unit5.Register Description5.3 4 MHz Timer Data Register (24 bits) (CUTR)The Timer Data Register (CUTR) holds the

973Chapter 50 Subclock Calibration Unit6.Application Note6. Application NoteThis section lists application notes concerning accuracy of the calibrat

83Chapter 3 MB91460 Series Basic Information6.Pin DefinitionsD26 125 105 P15_2 - OCU2 TOT2 - TP00_0 U/D CH / A Stop - 4mAC26 124 104 P15_1 - OCU1 TOT1

974Chapter 50 Subclock Calibration Unit6.Application Note Accuracy:The accuracy of the calibration is dependent on the clock frequency used by the 4

975Chapter 51 Low Voltage Reset/Interrupt1.OverviewChapter 51 Low Voltage Reset/Interrupt1. Overview• Module for generating a low voltage reset or i

976Chapter 51 Low Voltage Reset/Interrupt3.Registers3. Registers3.1 LV Detection Control RegistersControls the low voltage detection function.• LVD

977Chapter 51 Low Voltage Reset/Interrupt3.Registers• LVSEL: Address 04C4h (Access: Byte, Halfword, Word)(See “Meaning of Bit Attribute Symbols (Page

978Chapter 51 Low Voltage Reset/Interrupt3.Registers

979Chapter 52 Regulator Control1.OverviewChapter 52 Regulator Control1. Overview• Module for controlling the behaviour of the MAIN-Regulator and SUB

980Chapter 52 Regulator Control3.Registers3. Registers3.1 Regulator Control RegistersControls the regulator function.• REGCTR: Address 04CFh (Acces

981Chapter 52 Regulator Control3.Registers• REGSEL: Address 04CEh (Access: Byte, Halfword, Word)(See “Meaning of Bit Attribute Symbols (Page No.10)”

982Chapter 52 Regulator Control3.Registers

983Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM1.OverviewChapter 53 Fixed Mode-Reset Vector / BOOT-ROM1. OverviewThe Boot ROM is a fixed start-up ro